John M. Wilson

Orcid: 0000-0001-8488-3020

Affiliations:
  • NVIDIA Corporation, Durham, NC, USA
  • North Carolina State University, Raleigh, USA (former)


According to our database1, John M. Wilson authored at least 28 papers between 1999 and 2024.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

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PhD thesis 
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Links

Online presence:

On csauthors.net:

Bibliography

2024
A 0.190-pJ/bit 25.2-Gb/s/wire Inverter-Based AC-Coupled Transceiver for Short-Reach Die-to-Die Interfaces in 5-nm CMOS.
IEEE J. Solid State Circuits, April, 2024

Leveraging Micro-Bump Pitch Scaling to Accelerate Interposer Link Bandwidths for Future High-Performance Compute Applications.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2024

2023
A 0.297-pJ/Bit 50.4-Gb/s/Wire Inverter-Based Short-Reach Simultaneous Bi-Directional Transceiver for Die-to-Die Interface in 5-nm CMOS.
IEEE J. Solid State Circuits, 2023

2022
A 0.297-pJ/bit 50.4-Gb/s/wire Inverter-Based Short-Reach Simultaneous Bidirectional Transceiver for Die-to-Die Interface in 5nm CMOS.
Proceedings of the IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits 2022), 2022

2020
6.6 Reference-Noise Compensation Scheme for Single-Ended Package-to-Package Links.
Proceedings of the 2020 IEEE International Solid- State Circuits Conference, 2020

2019
A 1.17-pJ/b, 25-Gb/s/pin Ground-Referenced Single-Ended Serial Link for Off- and On-Package Communication Using a Process- and Temperature-Adaptive Voltage Regulator.
IEEE J. Solid State Circuits, 2019

A 2-to-20 GHz Multi-Phase Clock Generator with Phase Interpolators Using Injection-Locked Oscillation Buffers for High-Speed IOs in 16nm FinFET.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2019

2018
Hardware-Enabled Artificial Intelligence.
Proceedings of the 2018 IEEE Symposium on VLSI Circuits, 2018

A 1.17pJ/b 25Gb/s/pin ground-referenced single-ended serial link for off- and on-package communication in 16nm CMOS using a process- and temperature-adaptive voltage regulator.
Proceedings of the 2018 IEEE International Solid-State Circuits Conference, 2018

Ground-referenced signaling for intra-chip and short-reach chip-to-chip interconnects.
Proceedings of the 2018 IEEE Custom Integrated Circuits Conference, 2018

A switching linear regulator based on a fast-self-clocked comparator with very low probability of meta-stability and a parallel analog ripple control module.
Proceedings of the 2018 IEEE Custom Integrated Circuits Conference, 2018

2017
Fine-grained DRAM: energy-efficient DRAM for extreme bandwidth systems.
Proceedings of the 50th Annual IEEE/ACM International Symposium on Microarchitecture, 2017

A 25 Gb/s 470 μW active inductor equalizer for ground referenced signaling receivers.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2017

2016
8.6 A 6.5-to-23.3fJ/b/mm balanced charge-recycling bus in 16nm FinFET CMOS at 1.7-to-2.6Gb/s/wire with clock forwarding and low-crosstalk contraflow wiring.
Proceedings of the 2016 IEEE International Solid-State Circuits Conference, 2016

2013
A 0.54 pJ/b 20 Gb/s Ground-Referenced Single-Ended Short-Reach Serial Link in 28 nm CMOS for Advanced Packaging Applications.
IEEE J. Solid State Circuits, 2013

2011
Power-efficient I/O design considerations for high-bandwidth applications.
Proceedings of the 2011 IEEE Custom Integrated Circuits Conference, 2011

2010
A 4.3 GB/s Mobile Memory Interface With Power-Efficient Bandwidth Scaling.
IEEE J. Solid State Circuits, 2010

Thermal isolation in 3D chip stacks using vacuum gaps and capacitive or inductive communications.
Proceedings of the IEEE International Conference on 3D System Integration, 2010

2009
A 32-Gb/s On-Chip Bus With Driver Pre-Emphasis Signaling.
IEEE Trans. Very Large Scale Integr. Syst., 2009

2007
Voltage-Mode Driver Preemphasis Technique For On-Chip Global Buses.
IEEE Trans. Very Large Scale Integr. Syst., 2007

2006
3 gb/s AC coupled chip-to-chip communication using a low swing pulse receiver.
IEEE J. Solid State Circuits, 2006

A 32Gb/s On-chip Bus with Driver Pre-emphasis Signaling.
Proceedings of the IEEE 2006 Custom Integrated Circuits Conference, 2006

A 36Gb/s ACCI Multi-Channel Bus using a Fully Differential Pulse Receiver.
Proceedings of the IEEE 2006 Custom Integrated Circuits Conference, 2006

2005
Demystifying 3D ICs: The Pros and Cons of Going Vertical.
IEEE Des. Test Comput., 2005

Driver pre-emphasis techniques for on-chip global buses.
Proceedings of the 2005 International Symposium on Low Power Electronics and Design, 2005

2004
Simplified delay design guidelines for on-chip global interconnects.
Proceedings of the 14th ACM Great Lakes Symposium on VLSI 2004, 2004

2002
4 Gbps high-density AC coupled interconnection.
Proceedings of the IEEE 2002 Custom Integrated Circuits Conference, 2002

1999
MEMS-Based Capacitor Arrays for Programmable Interconnect and RF Applications.
Proceedings of the 18th Conference on Advanced Research in VLSI (ARVLSI '99), 1999


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