C. Thomas Gray

Orcid: 0000-0002-5137-5617

According to our database1, C. Thomas Gray authored at least 42 papers between 1990 and 2024.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

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Links

On csauthors.net:

Bibliography

2024
A 0.190-pJ/bit 25.2-Gb/s/wire Inverter-Based AC-Coupled Transceiver for Short-Reach Die-to-Die Interfaces in 5-nm CMOS.
IEEE J. Solid State Circuits, April, 2024

16.4 High-Density and Low-Power PUF Designs in 5nm Achieving 23× and 39× BER Reduction After Unstable Bit Detection and Masking.
Proceedings of the IEEE International Solid-State Circuits Conference, 2024

Leveraging Micro-Bump Pitch Scaling to Accelerate Interposer Link Bandwidths for Future High-Performance Compute Applications.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2024

A Distributed Power Supply Scheme with Dropout Voltage in Range 6mv-500mv and a Low Overhead Retention Mode.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2024

2023
A 0.297-pJ/Bit 50.4-Gb/s/Wire Inverter-Based Short-Reach Simultaneous Bi-Directional Transceiver for Die-to-Die Interface in 5-nm CMOS.
IEEE J. Solid State Circuits, 2023

A 95.6-TOPS/W Deep Learning Inference Accelerator With Per-Vector Scaled 4-bit Quantization in 5 nm.
IEEE J. Solid State Circuits, 2023

2022
An On-Chip Relaxation Oscillator in 5-nm FinFET Using a Frequency-Error Feedback Loop.
IEEE J. Solid State Circuits, 2022

An FLL-Based Clock Glitch Detector for Security Circuits in a 5nm FINFET Process.
Proceedings of the IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits 2022), 2022

A 0.297-pJ/bit 50.4-Gb/s/wire Inverter-Based Short-Reach Simultaneous Bidirectional Transceiver for Die-to-Die Interface in 5nm CMOS.
Proceedings of the IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits 2022), 2022

A 17-95.6 TOPS/W Deep Learning Inference Accelerator with Per-Vector Scaled 4-bit Quantization for Transformers in 5nm.
Proceedings of the IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits 2022), 2022

AutoCRAFT: Layout Automation for Custom Circuits in Advanced FinFET Technologies.
Proceedings of the ISPD 2022: International Symposium on Physical Design, Virtual Event, Canada, March 27, 2022

2021
Simba: scaling deep-learning inference with chiplet-based architecture.
Commun. ACM, 2021

A 77 MHz Relaxation Oscillator in 5nm FinFET with 3ns TIE over 10K cycles and ±0.3% Thermal Stability using Frequency-Error Feedback Loop.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2021

2020
A 0.32-128 TOPS, Scalable Multi-Chip-Module-Based Deep Neural Network Inference Accelerator With Ground-Referenced Signaling in 16 nm.
IEEE J. Solid State Circuits, 2020

6.6 Reference-Noise Compensation Scheme for Single-Ended Package-to-Package Links.
Proceedings of the 2020 IEEE International Solid- State Circuits Conference, 2020

2019
A 1.17-pJ/b, 25-Gb/s/pin Ground-Referenced Single-Ended Serial Link for Off- and On-Package Communication Using a Process- and Temperature-Adaptive Voltage Regulator.
IEEE J. Solid State Circuits, 2019

A 0.11 pJ/Op, 0.32-128 TOPS, Scalable Multi-Chip-Module-based Deep Neural Network Accelerator with Ground-Reference Signaling in 16nm.
Proceedings of the 2019 Symposium on VLSI Circuits, Kyoto, Japan, June 9-14, 2019, 2019

Simba: Scaling Deep-Learning Inference with Multi-Chip-Module-Based Architecture.
Proceedings of the 52nd Annual IEEE/ACM International Symposium on Microarchitecture, 2019

A 0.11 PJ/OP, 0.32-128 Tops, Scalable Multi-Chip-Module-Based Deep Neural Network Accelerator Designed with A High-Productivity vlsi Methodology.
Proceedings of the 2019 IEEE Hot Chips 31 Symposium (HCS), 2019

Analog/Mixed-Signal Hardware Error Modeling for Deep Learning Inference.
Proceedings of the 56th Annual Design Automation Conference 2019, 2019

A 2-to-20 GHz Multi-Phase Clock Generator with Phase Interpolators Using Injection-Locked Oscillation Buffers for High-Speed IOs in 16nm FinFET.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2019

Voltage-Follower Coupling Quadrature Oscillator with Embedded Phase-Interpolator in 16nm FinFET.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2019

2018
Hardware-Enabled Artificial Intelligence.
Proceedings of the 2018 IEEE Symposium on VLSI Circuits, 2018

A 1.17pJ/b 25Gb/s/pin ground-referenced single-ended serial link for off- and on-package communication in 16nm CMOS using a process- and temperature-adaptive voltage regulator.
Proceedings of the 2018 IEEE International Solid-State Circuits Conference, 2018

Ground-referenced signaling for intra-chip and short-reach chip-to-chip interconnects.
Proceedings of the 2018 IEEE Custom Integrated Circuits Conference, 2018

A switching linear regulator based on a fast-self-clocked comparator with very low probability of meta-stability and a parallel analog ripple control module.
Proceedings of the 2018 IEEE Custom Integrated Circuits Conference, 2018

2017
A 25 Gb/s 470 μW active inductor equalizer for ground referenced signaling receivers.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2017

A 256kb 6T self-tuning SRAM with extended 0.38V-1.2V operating range using multiple read/write assists and VMIN tracking canary sensors.
Proceedings of the 2017 IEEE Custom Integrated Circuits Conference, 2017

2016
A 28 nm 2 Mbit 6 T SRAM With Highly Configurable Low-Voltage Write-Ability Assist Implementation and Capacitor-Based Sense-Amplifier Input Offset Compensation.
IEEE J. Solid State Circuits, 2016

8.6 A 6.5-to-23.3fJ/b/mm balanced charge-recycling bus in 16nm FinFET CMOS at 1.7-to-2.6Gb/s/wire with clock forwarding and low-crosstalk contraflow wiring.
Proceedings of the 2016 IEEE International Solid-State Circuits Conference, 2016

2014
A reverse write assist circuit for SRAM dynamic write VMIN tracking using canary SRAMs.
Proceedings of the Fifteenth International Symposium on Quality Electronic Design, 2014

2013
A 0.54 pJ/b 20 Gb/s Ground-Referenced Single-Ended Short-Reach Serial Link in 28 nm CMOS for Advanced Packaging Applications.
IEEE J. Solid State Circuits, 2013

A 0.54pJ/b 20Gb/s ground-referenced single-ended short-haul serial link in 28nm CMOS for advanced packaging applications.
Proceedings of the 2013 IEEE International Solid-State Circuits Conference, 2013

2001
A DSP based 10BaseT/100BaseTX Ethernet transceiver in a 1.8 V, 0.18 μm CMOS technology.
Proceedings of the IEEE 2001 Custom Integrated Circuits Conference, 2001

1995
Concurrent timing optimization of latch-based digital systems.
Proceedings of the 1995 International Conference on Computer Design (ICCD '95), 1995

1994
A 250-MHz wave pipelined adder in 2-μm CMOS.
IEEE J. Solid State Circuits, September, 1994

A sampling technique and its CMOS implementation with 1 Gb/s bandwidth and 25 ps resolution.
IEEE J. Solid State Circuits, March, 1994

Timing constraints for wave-pipelined systems.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1994

Circuit delay calculation considering data dependent delays.
Integr., 1994

1991
Theoretical and Practical Issues in CMOS Wave Pipelining.
Proceedings of the VLSI 91, 1991

1990
P<sup>3</sup>A: a partitionable parallel/pipeline architecture for real-time image processing.
Proceedings of the 10th IAPR International Conference on Pattern Recognition, 1990

The design of a high-performance scalable architecture for image processing applications.
Proceedings of the Application Specific Array Processors, 1990


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