William Rhett Davis

Orcid: 0000-0002-9338-1441

According to our database1, William Rhett Davis authored at least 63 papers between 2001 and 2024.

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Bibliography

2024
DE-HNN: An effective neural model for Circuit Netlist representation.
CoRR, 2024

DE-HNN: An effective neural model for Circuit Netlist representation.
Proceedings of the International Conference on Artificial Intelligence and Statistics, 2024

2023
A Deep Transfer Learning Design Rule Checker With Synthetic Training.
IEEE Des. Test, February, 2023

2021
Fast and Accurate PPA Modeling with Transfer Learning.
Proceedings of the 3rd ACM/IEEE Workshop on Machine Learning for CAD, 2021

An Instruction-Level Power and Energy Model for the Rocket Chip Generator.
Proceedings of the IEEE/ACM International Symposium on Low Power Electronics and Design, 2021

Fast and Accurate PPA Modeling with Transfer Learning.
Proceedings of the IEEE/ACM International Conference On Computer Aided Design, 2021

A Virtual Platform for Object Detection Systems.
Proceedings of the IEEE International 3D Systems Integration Conference, 2021

2020
Development of a Predictive Process Design kit for15-nm FinFETs: FreePDK15.
CoRR, 2020

Design Rule Checking with a CNN Based Feature Extractor.
Proceedings of the MLCAD '20: 2020 ACM/IEEE Workshop on Machine Learning for CAD, 2020

How to write a compact reliability model with the Open Model Interface (OMI).
Proceedings of the 2020 IEEE International Reliability Physics Symposium, 2020

2019
3-D-DATE: A Circuit-Level Three-Dimensional DRAM Area, Timing, and Energy Model.
IEEE Trans. Circuits Syst. I Regul. Pap., 2019

Estimating Pareto Optimum Fronts to Determine Knob Settings in Electronic Design Automation Tools.
Proceedings of the 20th International Symposium on Quality Electronic Design, 2019

Characterization of Fast, Accurate Leakage Power Models for IEEE P2416.
Proceedings of the 20th International Symposium on Quality Electronic Design, 2019

Vertical Stack Thermal Characterization of Heterogeneous Integration and Packages.
Proceedings of the 2019 International 3D Systems Integration Conference (3DIC), 2019

2017
H3 (Heterogeneity in 3D): A Logic-on-Logic 3D-Stacked Heterogeneous Multi-Core Processor.
Proceedings of the 2017 IEEE International Conference on Computer Design, 2017

2016
Physical design of a 3D-stacked heterogeneous multi-core processor.
Proceedings of the 2016 IEEE International 3D Systems Integration Conference, 2016

2015
FreePDK15: An Open-Source Predictive Process Design Kit for 15nm FinFET Technology.
Proceedings of the 2015 Symposium on International Symposium on Physical Design, ISPD 2015, Monterey, CA, USA, March 29, 2015

Under 100-cycle thread migration latency in a single-ISA heterogeneous multi-core processor.
Proceedings of the 2015 IEEE Hot Chips 27 Symposium (HCS), 2015

Computing in 3D.
Proceedings of the 2015 IEEE Custom Integrated Circuits Conference, 2015

Thermal simulation of heterogeneous GaN/ InP/silicon 3DIC stacks.
Proceedings of the 2015 International 3D Systems Integration Conference, 2015

Computing in 3D.
Proceedings of the 2015 International 3D Systems Integration Conference, 2015

2014
Pathfinder3D: A framework for exploring early thermal tradeoffs in 3DIC.
Proceedings of the 2014 IEEE International Conference on IC Design & Technology, 2014

Towards a standard flow for system level power modeling.
Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, 2014

Leveraging 3D-IC for on-chip timing uncertainty measurements.
Proceedings of the 2014 International 3D Systems Integration Conference, 2014

Thermal effects of heterogeneous interconnects on InP / GaN / Si diverse integrated circuits.
Proceedings of the 2014 International 3D Systems Integration Conference, 2014

3D-enabled customizable embedded computer (3DECC).
Proceedings of the 2014 International 3D Systems Integration Conference, 2014

2013
Hetero<sup>2</sup> 3D integration: A scheme for optimizing efficiency/cost of Chip Multiprocessors.
Proceedings of the International Symposium on Quality Electronic Design, 2013

Exploring early design tradeoffs in 3DIC.
Proceedings of the 2013 IEEE International Symposium on Circuits and Systems (ISCAS2013), 2013

Rationale for a 3D heterogeneous multi-core processor.
Proceedings of the 2013 IEEE 31st International Conference on Computer Design, 2013

Design of controller for L2 cache mapped in Tezzaron stacked DRAM.
Proceedings of the 2013 IEEE International 3D Systems Integration Conference (3DIC), 2013

2012
Area-Efficient Antenna-Scalable MIMO Detector for K-best Sphere Decoding.
J. Signal Process. Syst., 2012

Parallel Transient Simulation of Multiphysics Circuits Using Delay-Based Partitioning.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2012

Junction-Level Thermal Analysis of 3-D Integrated Circuits Using High Definition Power Blurring.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2012

Dynamic electrothermal simulation of three-dimensional integrated circuits using standard cell macromodels.
IET Circuits Devices Syst., 2012

Leakage Power Contributor Modeling.
IEEE Des. Test Comput., 2012

2011
Design and Computer Aided Design of 3DIC.
Proceedings of the 3D Integration for NoC-based SoC Architectures, 2011

3D specific systems design and CAD.
Proceedings of the 2011 International Conference on Embedded Computer Systems: Architectures, 2011

An energy-efficient 64-QAM MIMO detector for emerging wireless standards.
Proceedings of the Design, Automation and Test in Europe, 2011

Pathfinder 3D: A flow for system-level design space exploration.
Proceedings of the 2011 IEEE International 3D Systems Integration Conference (3DIC), Osaka, Japan, January 31, 2011

Coordinating 3D designs: Interface IP, standards or free form?
Proceedings of the 2011 IEEE International 3D Systems Integration Conference (3DIC), Osaka, Japan, January 31, 2011

2010
Low-Power Hypercube Divided Memory FFT Engine Using 3D Integration.
ACM Trans. Design Autom. Electr. Syst., 2010

Algorithm and hardware complexity reduction techniques for k-best sphere decoders.
Proceedings of the 20th ACM Great Lakes Symposium on VLSI 2009, 2010

A low-area flexible MIMO detector for WiFi/WiMAX standards.
Proceedings of the Design, Automation and Test in Europe, 2010

Creating 3D specific systems: Architecture, design and CAD.
Proceedings of the Design, Automation and Test in Europe, 2010

2009
Automated Design Space Exploration for DSP Applications.
J. Signal Process. Syst., 2009

Application Exploration for 3-D Integrated Circuits: TCAM, FIFO, and FFT Case Studies.
IEEE Trans. Very Large Scale Integr. Syst., 2009

High-throughput low-complexity MIMO detector based on K-best algorithm.
Proceedings of the 19th ACM Great Lakes Symposium on VLSI 2009, 2009

The benefits of 3D networks-on-chip as shown with LDPC decoding.
Proceedings of the IEEE International Conference on 3D System Integration, 2009

Junction-level thermal extraction and simulation of 3DICs.
Proceedings of the IEEE International Conference on 3D System Integration, 2009

Delay analysis and design exploration for 3D SRAM.
Proceedings of the IEEE International Conference on 3D System Integration, 2009

2008
Design and CAD for 3D integrated circuits.
Proceedings of the 45th Design Automation Conference, 2008

Inter-die signaling in three dimensional integrated circuits.
Proceedings of the IEEE 2008 Custom Integrated Circuits Conference, 2008

2007
FreePDK: An Open-Source Variation-Aware Design Kit.
Proceedings of the IEEE International Conference on Microelectronic Systems Education, 2007

An architecture for energy efficient sphere decoding.
Proceedings of the 2007 International Symposium on Low Power Electronics and Design, 2007

2006
Architecture for Energy Efficient Sphere Decoding.
Proceedings of the 2006 IEEE International SOC Conference, Austin, Texas, USA, 2006

Automated Architectural Exploration for Signal Processing Algorithms.
Proceedings of the IEEE Workshop on Signal Processing Systems, 2006

Exploring compromises among timing, power and temperature in three-dimensional integrated circuits.
Proceedings of the 43rd Design Automation Conference, 2006

2005
Demystifying 3D ICs: The Pros and Cons of Going Vertical.
IEEE Des. Test Comput., 2005

2004
Multi-Parameter Power Minimization of Synthesized Datapaths.
Proceedings of the 2004 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2004), 2004

2003
A 500-Mb/s soft-output Viterbi decoder.
IEEE J. Solid State Circuits, 2003

Getting High-Performance Silicon from System-Level Design.
Proceedings of the 2003 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2003), 2003

2002
A design environment for high-throughput low-power dedicated signal processing systems.
IEEE J. Solid State Circuits, 2002

2001
A design environment for high throughput, low power dedicated signal processing systems.
Proceedings of the IEEE 2001 Custom Integrated Circuits Conference, 2001


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