Walker J. Turner

Orcid: 0000-0001-9230-7605

According to our database1, Walker J. Turner authored at least 19 papers between 2014 and 2024.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

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Links

On csauthors.net:

Bibliography

2024
A 0.190-pJ/bit 25.2-Gb/s/wire Inverter-Based AC-Coupled Transceiver for Short-Reach Die-to-Die Interfaces in 5-nm CMOS.
IEEE J. Solid State Circuits, April, 2024

Leveraging Micro-Bump Pitch Scaling to Accelerate Interposer Link Bandwidths for Future High-Performance Compute Applications.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2024

2023
A 0.297-pJ/Bit 50.4-Gb/s/Wire Inverter-Based Short-Reach Simultaneous Bi-Directional Transceiver for Die-to-Die Interface in 5-nm CMOS.
IEEE J. Solid State Circuits, 2023

Reinforcement Learning Guided Detailed Routing for Custom Circuits.
Proceedings of the 2023 International Symposium on Physical Design, 2023

2022
An On-Chip Relaxation Oscillator in 5-nm FinFET Using a Frequency-Error Feedback Loop.
IEEE J. Solid State Circuits, 2022

A 0.297-pJ/bit 50.4-Gb/s/wire Inverter-Based Short-Reach Simultaneous Bidirectional Transceiver for Die-to-Die Interface in 5nm CMOS.
Proceedings of the IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits 2022), 2022

AutoCRAFT: Layout Automation for Custom Circuits in Advanced FinFET Technologies.
Proceedings of the ISPD 2022: International Symposium on Physical Design, Virtual Event, Canada, March 27, 2022

TAG: Learning Circuit Spatial Embedding from Layouts.
Proceedings of the 41st IEEE/ACM International Conference on Computer-Aided Design, 2022

Routability-Aware Placement for Advanced FinFET Mixed-Signal Circuits using Satisfiability Modulo Theories.
Proceedings of the 2022 Design, Automation & Test in Europe Conference & Exhibition, 2022

2021
Parasitic-Aware Analog Circuit Sizing with Graph Neural Networks and Bayesian Optimization.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2021

A 77 MHz Relaxation Oscillator in 5nm FinFET with 3ns TIE over 10K cycles and ±0.3% Thermal Stability using Frequency-Error Feedback Loop.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2021

2020
6.6 Reference-Noise Compensation Scheme for Single-Ended Package-to-Package Links.
Proceedings of the 2020 IEEE International Solid- State Circuits Conference, 2020

ParaGraph: Layout Parasitics and Device Parameter Prediction using Graph Neural Networks.
Proceedings of the 57th ACM/IEEE Design Automation Conference, 2020

2019
A 1.17-pJ/b, 25-Gb/s/pin Ground-Referenced Single-Ended Serial Link for Off- and On-Package Communication Using a Process- and Temperature-Adaptive Voltage Regulator.
IEEE J. Solid State Circuits, 2019

A 2-to-20 GHz Multi-Phase Clock Generator with Phase Interpolators Using Injection-Locked Oscillation Buffers for High-Speed IOs in 16nm FinFET.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2019

2018
A 1.17pJ/b 25Gb/s/pin ground-referenced single-ended serial link for off- and on-package communication in 16nm CMOS using a process- and temperature-adaptive voltage regulator.
Proceedings of the 2018 IEEE International Solid-State Circuits Conference, 2018

Ground-referenced signaling for intra-chip and short-reach chip-to-chip interconnects.
Proceedings of the 2018 IEEE Custom Integrated Circuits Conference, 2018

2016
A 4.7 T/11.1 T NMR Compliant 50 nW Wirelessly Programmable Implant for Bioartificial Pancreas In Vivo Monitoring.
IEEE J. Solid State Circuits, 2016

2014
A 4.7T/11.1T NMR compliant wirelessly programmable implant for bio-artificial pancreas in vivo monitoring.
Proceedings of the Symposium on VLSI Circuits, 2014


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