John Poulton

Orcid: 0000-0002-1722-7637

Affiliations:
  • NVIDIA Inc., Durham, NC, USA
  • PhD University of North Carolina, Chapel Hill, NC, USA (1980)


According to our database1, John Poulton authored at least 43 papers between 1983 and 2024.

Collaborative distances:

Awards

IEEE Fellow

IEEE Fellow 2012, "For contributions to high-speed low-power signaling and to graphics architecture".

Timeline

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Links

Online presence:

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Bibliography

2024
A 0.190-pJ/bit 25.2-Gb/s/wire Inverter-Based AC-Coupled Transceiver for Short-Reach Die-to-Die Interfaces in 5-nm CMOS.
IEEE J. Solid State Circuits, April, 2024

Leveraging Micro-Bump Pitch Scaling to Accelerate Interposer Link Bandwidths for Future High-Performance Compute Applications.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2024

2023
A 0.297-pJ/Bit 50.4-Gb/s/Wire Inverter-Based Short-Reach Simultaneous Bi-Directional Transceiver for Die-to-Die Interface in 5-nm CMOS.
IEEE J. Solid State Circuits, 2023

2022
A 0.297-pJ/bit 50.4-Gb/s/wire Inverter-Based Short-Reach Simultaneous Bidirectional Transceiver for Die-to-Die Interface in 5nm CMOS.
Proceedings of the IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits 2022), 2022

2020
6.6 Reference-Noise Compensation Scheme for Single-Ended Package-to-Package Links.
Proceedings of the 2020 IEEE International Solid- State Circuits Conference, 2020

2019
A 1.17-pJ/b, 25-Gb/s/pin Ground-Referenced Single-Ended Serial Link for Off- and On-Package Communication Using a Process- and Temperature-Adaptive Voltage Regulator.
IEEE J. Solid State Circuits, 2019

A 2-to-20 GHz Multi-Phase Clock Generator with Phase Interpolators Using Injection-Locked Oscillation Buffers for High-Speed IOs in 16nm FinFET.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2019

Voltage-Follower Coupling Quadrature Oscillator with Embedded Phase-Interpolator in 16nm FinFET.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2019

2018
Hardware-Enabled Artificial Intelligence.
Proceedings of the 2018 IEEE Symposium on VLSI Circuits, 2018

A 1.17pJ/b 25Gb/s/pin ground-referenced single-ended serial link for off- and on-package communication in 16nm CMOS using a process- and temperature-adaptive voltage regulator.
Proceedings of the 2018 IEEE International Solid-State Circuits Conference, 2018

Ground-referenced signaling for intra-chip and short-reach chip-to-chip interconnects.
Proceedings of the 2018 IEEE Custom Integrated Circuits Conference, 2018

A switching linear regulator based on a fast-self-clocked comparator with very low probability of meta-stability and a parallel analog ripple control module.
Proceedings of the 2018 IEEE Custom Integrated Circuits Conference, 2018

2017
A 25 Gb/s 470 μW active inductor equalizer for ground referenced signaling receivers.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2017

A 256kb 6T self-tuning SRAM with extended 0.38V-1.2V operating range using multiple read/write assists and VMIN tracking canary sensors.
Proceedings of the 2017 IEEE Custom Integrated Circuits Conference, 2017

2016
A 28 nm 2 Mbit 6 T SRAM With Highly Configurable Low-Voltage Write-Ability Assist Implementation and Capacitor-Based Sense-Amplifier Input Offset Compensation.
IEEE J. Solid State Circuits, 2016

8.6 A 6.5-to-23.3fJ/b/mm balanced charge-recycling bus in 16nm FinFET CMOS at 1.7-to-2.6Gb/s/wire with clock forwarding and low-crosstalk contraflow wiring.
Proceedings of the 2016 IEEE International Solid-State Circuits Conference, 2016

2014
A reverse write assist circuit for SRAM dynamic write VMIN tracking using canary SRAMs.
Proceedings of the Fifteenth International Symposium on Quality Electronic Design, 2014

2013
A 0.54 pJ/b 20 Gb/s Ground-Referenced Single-Ended Short-Reach Serial Link in 28 nm CMOS for Advanced Packaging Applications.
IEEE J. Solid State Circuits, 2013

A 0.54pJ/b 20Gb/s ground-referenced single-ended short-haul serial link in 28nm CMOS for advanced packaging applications.
Proceedings of the 2013 IEEE International Solid-State Circuits Conference, 2013

2010
A 4.3 GB/s Mobile Memory Interface With Power-Efficient Bandwidth Scaling.
IEEE J. Solid State Circuits, 2010

2007
A 14-mW 6.25-Gb/s Transceiver in 90-nm CMOS.
IEEE J. Solid State Circuits, 2007

A 14mW 6.25Gb/s Transceiver in 90nm CMOS for Serial Chip-to-Chip Communications.
Proceedings of the 2007 IEEE International Solid-State Circuits Conference, 2007

2006
A CMOS mixed-signal clock and data recovery circuit for OIF CEI-6G+ backplane transceiver.
IEEE J. Solid State Circuits, 2006

2004
The design of DNA self-assembled computing circuitry.
IEEE Trans. Very Large Scale Integr. Syst., 2004

A 33-mW 8-Gb/s CMOS clock multiplier and CDR for highly integrated I/Os.
IEEE J. Solid State Circuits, 2004

2003
A second-order semidigital clock recovery circuit based on injection locking.
IEEE J. Solid State Circuits, 2003

Jitter transfer characteristics of delay-locked loops - theories and design techniques.
IEEE J. Solid State Circuits, 2003

CMOS High-Speed I/Os - Present and Future.
Proceedings of the 21st International Conference on Computer Design (ICCD 2003), 2003

A 33mW 8Gb/s CMOS clock multiplier and CDR for highly integrated I/Os.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2003

2002
A low-power multiplying DLL for low-jitter multigigahertz clock generation in highly integrated digital chips.
IEEE J. Solid State Circuits, 2002

2001
Digital systems engineering.
Cambridge University Press, ISBN: 978-0-521-59292-5, 2001

1999
Problems and Prospects for Electrical Signaling.
Proceedings of the 18th Conference on Advanced Research in VLSI (ARVLSI '99), 1999

1998
A tracking clock recovery receiver for 4-Gbps signaling.
IEEE Micro, 1998

1997
Transmitter equalization for 4-Gbps signaling.
IEEE Micro, 1997

PixelFlow: The Realization.
Proceedings of the 1997 ACM SIGGRAPH/EUROGRAPHICS Workshop on Graphics Hardware, 1997

An Embedded DRAM for CMOS ASICs.
Proceedings of the 17th Conference on Advanced Research in VLSI (ARVLSI '97), 1997

1992
Breaking the frame-buffer bottleneck with logic-enhanced memories.
IEEE Computer Graphics and Applications, 1992

PixelFlow: high-speed rendering using image composition.
Proceedings of the 19th Annual Conference on Computer Graphics and Interactive Techniques, 1992

1989
Pixel-planes 5: a heterogeneous multiprocessor graphics system using processor-enhanced memories.
Proceedings of the 16th Annual Conference on Computer Graphics and Interactive Techniques, 1989

1987
Pixel-Planes 4: A Summary.
Proceedings of the Advances in Computer Graphics Hardware II (Eurographics'87 Workshop), 1987

1985
Fast spheres, shadows, textures, transparencies, and imgage enhancements in pixel-planes.
Proceedings of the 12th Annual Conference on Computer Graphics and Interactive Techniques, 1985

Fast Spheres, Shadows, Textures, Transparencies, and Image Enhancements in Pixel-Planes.
Proceedings of the Advances in Computer Graphics I (Tutorials from Eurographics'84 and Eurographics'85 Conf.), 1985

1983
A vertically integrated VLSI design environment.
Proceedings of the 20th Design Automation Conference, 1983


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