J. P. Bastos

According to our database1, J. P. Bastos authored at least 5 papers between 2022 and 2024.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

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Links

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Bibliography

2024
Investigation of the Impact of Ferroelectricity Boosted Gate Stacks for 3D NAND on Short Time Data Retention and Endurance.
Proceedings of the IEEE International Reliability Physics Symposium, 2024

Side and Corner Region Non-Uniformities in Grown SiO2 and Their Implications on Current, Capacitance and Breakdown Characteristics.
Proceedings of the IEEE International Reliability Physics Symposium, 2024

2022
High Performance Thermally Resistant FinFETs DRAM Peripheral CMOS FinFETs with VTH Tunability for Future Memories.
Proceedings of the IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits 2022), 2022

Bias Temperature Instability (BTI) of High-Voltage Devices for Memory Periphery.
Proceedings of the IEEE International Reliability Physics Symposium, 2022

High-K incorporated in a SiON tunnel layer for 3D NAND programming voltage reduction.
Proceedings of the IEEE International Memory Workshop, 2022


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