Tezaswi Raja

According to our database1, Tezaswi Raja authored at least 12 papers between 2003 and 2024.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Dataset
Other 

Links

On csauthors.net:

Bibliography

2024
A Distributed Power Supply Scheme with Dropout Voltage in Range 6mv-500mv and a Low Overhead Retention Mode.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2024

2019
A Fine-Grained GALS SoC with Pausible Adaptive Clocking in 16 nm FinFET.
Proceedings of the 25th IEEE International Symposium on Asynchronous Circuits and Systems, 2019

2015
An Energy-Recovering Reconfigurable Series Resonant Clocking Scheme for Wide Frequency Operation.
IEEE Trans. Circuits Syst. I Regul. Pap., 2015

2013
Low power low voltage wide frequency resonant clock and data circuits for power reductions.
Proceedings of the 4th IEEE Latin American Symposium on Circuits and Systems, 2013

2010
Digital Logic Implementation in Memristor-Based Crossbars - A Tutorial.
Proceedings of the Fifth IEEE International Symposium on Electronic Design, 2010

2009
Variable Input Delay CMOS Logic for Low Power Design.
IEEE Trans. Very Large Scale Integr. Syst., 2009

2006
Transistor Sizing of Logic Gates to Maximize Input Delay Variability.
J. Low Power Electron., 2006

2005
Design of Variable Input Delay Gates for Low Dynamic Power Circuits.
Proceedings of the Integrated Circuit and System Design, 2005

2004
CMOS Circuit Design for Minimum Dynamic Power and Highest Speed.
Proceedings of the 17th International Conference on VLSI Design (VLSI Design 2004), 2004

A Tuturial on the Emerging Nanotechnology Devices.
Proceedings of the 17th International Conference on VLSI Design (VLSI Design 2004), 2004

Using a Jini based desktop Grid for test vector compaction and a refined economic model.
Proceedings of the 4th IEEE/ACM International Symposium on Cluster Computing and the Grid (CCGrid 2004), 2004

2003
Minimum Dynamic Power CMOS Circuit Design by a Reduced Constraint Set Linear Program.
Proceedings of the 16th International Conference on VLSI Design (VLSI Design 2003), 2003


  Loading...