Sven Beyer

According to our database1, Sven Beyer authored at least 23 papers between 2003 and 2024.

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Bibliography

2024
Paving the Way for Pass Disturb Free Vertical NAND Storage via A Dedicated and String-Compatible Pass Gate.
CoRR, 2024

Reliability Assesement of Ferroelectric nvCAP for Small-Signal Capacitive Read-Out.
Proceedings of the IEEE International Reliability Physics Symposium, 2024

Performance and Reliability of Technology Qualified 34 Mb Split-Gate eFLASH Macro in 28 nm HKMG.
Proceedings of the IEEE International Memory Workshop, 2024

Charge trapping challenges of CMOS embedded complementary FeFETs.
Proceedings of the IEEE International Memory Workshop, 2024

2023
Demonstration of Differential Mode Ferroelectric Field-Effect Transistor Array-Based in-Memory Computing Macro for Realizing Multiprecision Mixed-Signal Artificial Intelligence Accelerator.
Adv. Intell. Syst., June, 2023

Ferroelectric MirrorBit-Integrated Field-Programmable Memory Array for TCAM, Storage, and In-Memory Computing Applications.
CoRR, 2023

Powering Disturb-Free Reconfigurable Computing and Tunable Analog Electronics with Dual-Port Ferroelectric FET.
CoRR, 2023

FeFET-based MirrorBit cell for High-density NVM storage.
CoRR, 2023

Multi-Level Operation of Ferroelectric FET Memory Arrays for Compute-In-Memory Applications.
Proceedings of the IEEE International Memory Workshop, 2023

2022
Ferroelectric FET based Context-Switching FPGA Enabling Dynamic Reconfiguration for Adaptive Deep Learning Machines.
CoRR, 2022

Asymmetric Double-Gate Ferroelectric FET to Decouple the Tradeoff Between Thickness Scaling and Memory Window.
Proceedings of the IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits 2022), 2022

Endurance improvements and defect characterization in ferroelectric FETs through interface fluorination.
Proceedings of the IEEE International Memory Workshop, 2022

Interfacial Layer Engineering to Enhance Noise Immunity of FeFETs for IMC Applications.
Proceedings of the International Conference on IC Design and Technology, 2022

2021
Hardware Functional Obfuscation With Ferroelectric Active Interconnects.
CoRR, 2021

Novel embedded single poly floating gate flash demonstrated in 22nm FDSOI technology.
Proceedings of the IEEE International Memory Workshop, 2021

2019
Performance Improvement on HfO2-Based 1T Ferroelectric NVM by Electrical Preconditioning.
Proceedings of the IEEE International Reliability Physics Symposium, 2019

Ultra-dense co-integration of FeFETs and CMOS logic enabling very-fine grained Logic-in-Memory.
Proceedings of the 49th European Solid-State Device Research Conference, 2019

2010
Automated formal verification of processors based on architectural models.
Proceedings of 10th International Conference on Formal Methods in Computer-Aided Design, 2010

2009
Generating an Efficient Instruction Set Simulator from a Complete Property Suite.
Proceedings of the Twentienth IEEE/IFIP International Symposium on Rapid System Prototyping, 2009

2006
Putting it all together - Formal verification of the VAMP.
Int. J. Softw. Tools Technol. Transf., 2006

2005
Putting it all together: formal verification of the VAMP.
PhD thesis, 2005

Towards the Formal Verification of Lower System Layers in Automotive Systems.
Proceedings of the 23rd International Conference on Computer Design (ICCD 2005), 2005

2003
Instantiating Uninterpreted Functional Units and Memory System: Functional Verification of the VAMP.
Proceedings of the Correct Hardware Design and Verification Methods, 2003


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