Farhad Merchant

Orcid: 0000-0002-3708-5621

According to our database¹, Farhad Merchant authored at least 63 papers between 2011 and 2024.

Collaborative distances:

Dijkstra number² of four.
Erdős number³ of three.

Timeline

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In proceedings

Article

PhD thesis

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Other

Bibliography

2024

Error Detection and Correction Codes for Safe In-Memory Computations.

[BibT_eX]

[DOI]

CoRR, 2024

QTFlow: Quantitative Timing-Sensitive Information Flow for Security-Aware Hardware Design on RTL.

[BibT_eX]

[DOI]

CoRR, 2024

Harnessing Entropy: RRAM Crossbar-based Unified PUF and RNG.

[BibT_eX]

[DOI]

Gokulnath Rajendran

Furqan Zahoor

Sidhaant Sachin Thakker

Proceedings of the 37th International Conference on VLSI Design and 23rd International Conference on Embedded Systems, 2024

Experimental Validation of Memristor-Aided Logic Using 1T1R TaOx RRAM Crossbar Array.

[BibT_eX]

[DOI]

Proceedings of the 37th International Conference on VLSI Design and 23rd International Conference on Embedded Systems, 2024

2023

FPGA-based Deep Learning Inference Accelerators: Where Are We Standing?

[BibT_eX]

[DOI]

ACM Trans. Reconfigurable Technol. Syst., December, 2023

Should We Even Optimize for Execution Energy? Rethinking Mapping for MAGIC Design Style.

[BibT_eX]

[DOI]

Simranjeet Singh

Chandan Kumar Jha

Ankit Bende

Phrangboklang Lyngton Thangkhiew

IEEE Embed. Syst. Lett., December, 2023

CLARINET: A quire-enabled RISC-V-based framework for posit arithmetic empiricism.

[BibT_eX]

[DOI]

Niraj N. Sharma

Riya Jain

Mohana Madhumita Pokkuluri

J. Syst. Archit., February, 2023

MemSPICE: Automated Simulation and Energy Estimation Framework for MAGIC-Based Logic-in-Memory.

[BibT_eX]

[DOI]

CoRR, 2023

SoftFlow: Automated HW-SW Confidentiality Verification for Embedded Processors.

[BibT_eX]

[DOI]

Proceedings of the 31st IFIP/IEEE International Conference on Very Large Scale Integration, 2023

PR-PUF: A Reconfigurable Strong RRAM PUF.

[BibT_eX]

[DOI]

Proceedings of the 31st IFIP/IEEE International Conference on Very Large Scale Integration, 2023

Integrated Architecture for Neural Networks and Security Primitives using RRAM Crossbar.

[BibT_eX]

[DOI]

Proceedings of the 21st IEEE Interregional NEWCAS Conference, 2023

Finite State Automata Design using 1T1R ReRAM Crossbar.

[BibT_eX]

[DOI]

Proceedings of the 21st IEEE Interregional NEWCAS Conference, 2023

Gate Camouflaging Using Reconfigurable ISFET-Based Threshold Voltage Defined Logic.

[BibT_eX]

[DOI]

Proceedings of the 21st IEEE Interregional NEWCAS Conference, 2023

Exploring Multi-Valued Logic and its Application in Emerging Post-CMOS Technologies.

[BibT_eX]

[DOI]

Proceedings of the 18th ACM International Symposium on Nanoscale Architectures, 2023

IMBUE: In-Memory Boolean-to-CUrrent Inference ArchitecturE for Tsetlin Machines.

[BibT_eX]

[DOI]

Proceedings of the IEEE/ACM International Symposium on Low Power Electronics and Design, 2023

DeepAttack: A Deep Learning Based Oracle-less Attack on Logic Locking.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Symposium on Circuits and Systems, 2023

Hardware Security Primitives Using Passive RRAM Crossbar Array: Novel TRNG and PUF Designs.

[BibT_eX]

[DOI]

Proceedings of the 28th Asia and South Pacific Design Automation Conference, 2023

2022

Deceptive Logic Locking for Hardware Integrity Protection Against Machine Learning Attacks.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022

A Survey of Neuromorphic Computing-in-Memory: Architectures, Simulators, and Security.

[BibT_eX]

[DOI]

Felix Staudigl

Farhad Merchant

Rainer Leupers

IEEE Des. Test, 2022

PA-PUF: A Novel Priority Arbiter PUF.

[BibT_eX]

[DOI]

Proceedings of the 30th IFIP/IEEE 30th International Conference on Very Large Scale Integration, 2022

A Temperature Independent Readout Circuit for ISFET-Based Sensor Applications.

[BibT_eX]

[DOI]

Proceedings of the 23rd IEEE Latin American Test Symposium, 2022

Security as an Important Ingredient in Neuromorphic Engineering.

[BibT_eX]

[DOI]

Farhad Merchant

Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2022

Discrete Steps towards Approximate Computing.

[BibT_eX]

[DOI]

Proceedings of the 23rd International Symposium on Quality Electronic Design, 2022

A Parallel SystemC Virtual Platform for Neuromorphic Architectures.

[BibT_eX]

[DOI]

Melvin Galicia

Farhad Merchant

Rainer Leupers

Proceedings of the 23rd International Symposium on Quality Electronic Design, 2022

pHGen: A pH-Based Key Generation Mechanism Using ISFETs.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Symposium on Hardware Oriented Security and Trust, 2022

NeuroHammer: Inducing Bit-Flips in Memristive Crossbar Memories.

[BibT_eX]

[DOI]

Proceedings of the 2022 Design, Automation & Test in Europe Conference & Exhibition, 2022

NEUROTEC I: Neuro-inspired Artificial Intelligence Technologies for the Electronics of the Future.

[BibT_eX]

[DOI]

Proceedings of the 2022 Design, Automation & Test in Europe Conference & Exhibition, 2022

2021

Challenging the Security of Logic Locking Schemes in the Era of Deep Learning: A Neuroevolutionary Approach.

[BibT_eX]

[DOI]

ACM J. Emerg. Technol. Comput. Syst., 2021

ExPAN(N)D: Exploring Posits for Efficient Artificial Neural Network Design in FPGA-Based Systems.

[BibT_eX]

[DOI]

IEEE Access, 2021

ANDROMEDA: An FPGA Based RISC-V MPSoC Exploration Framework.

[BibT_eX]

[DOI]

Proceedings of the 34th International Conference on VLSI Design and 20th International Conference on Embedded Systems, 2021

An Investigation on Inherent Robustness of Posit Data Representation.

[BibT_eX]

[DOI]

Proceedings of the 34th International Conference on VLSI Design and 20th International Conference on Embedded Systems, 2021

Logic Locking at the Frontiers of Machine Learning: A Survey on Developments and Opportunities.

[BibT_eX]

[DOI]

Proceedings of the 29th IFIP/IEEE International Conference on Very Large Scale Integration, 2021

Brightening the Optical Flow through Posit Arithmetic.

[BibT_eX]

[DOI]

Proceedings of the 22nd International Symposium on Quality Electronic Design, 2021

QFlow: Quantitative Information Flow for Security-Aware Hardware Design in Verilog.

[BibT_eX]

[DOI]

Proceedings of the 39th IEEE International Conference on Computer Design, 2021

Vertical IP Protection of the Next-Generation Devices: Quo Vadis?

[BibT_eX]

[DOI]

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2021

Nano Security: From Nano-Electronics to Secure Systems.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2021

2020

CLARINET: A RISC-V Based Framework for Posit Arithmetic Empiricism.

[BibT_eX]

[DOI]

CoRR, 2020

Accelerating Deep Learning Inference in Constrained Embedded Devices Using Hardware Loops and a Dot Product Unit.

[BibT_eX]

[DOI]

IEEE Access, 2020

A secure hardware-software solution based on RISC-V, logic locking and microkernel.

[BibT_eX]

[DOI]

Massimiliano Giacometti

Sascha Kegreiß

Proceedings of the SCOPES '20: 23rd International Workshop on Software and Compilers for Embedded Systems, 2020

Next Generation Arithmetic for Edge Computing.

[BibT_eX]

[DOI]

Proceedings of the 2020 Design, Automation & Test in Europe Conference & Exhibition, 2020

Scaling Logic Locking Schemes to Multi-module Hardware Designs.

[BibT_eX]

[DOI]

Proceedings of the Architecture of Computing Systems - ARCS 2020, 2020

2019

Applying Modified Householder Transform to Kalman Filter.

[BibT_eX]

[DOI]

Proceedings of the 32nd International Conference on VLSI Design and 18th International Conference on Embedded Systems, 2019

A Systematic Approach for Acceleration of Matrix-Vector Operations in CGRA through Algorithm-Architecture Co-Design.

[BibT_eX]

[DOI]

Proceedings of the 32nd International Conference on VLSI Design and 18th International Conference on Embedded Systems, 2019

A Critical Evaluation of the Paradigm Shift in the Design of Logic Encryption Algorithms.

[BibT_eX]

[DOI]

Proceedings of the International Symposium on VLSI Design, Automation and Test, 2019

Protecting the Integrity of Processor Cores with Logic Encryption.

[BibT_eX]

[DOI]

Dominik Sisejkovic

Farhad Merchant

Rainer Leupers

Proceedings of the 32nd IEEE International System-on-Chip Conference, 2019

Control-Lock: Securing Processor Cores Against Software-Controlled Hardware Trojans.

[BibT_eX]

[DOI]

Proceedings of the 2019 on Great Lakes Symposium on VLSI, 2019

Inter-Lock: Logic Encryption for Processor Cores Beyond Module Boundaries.

[BibT_eX]

[DOI]

Proceedings of the 24th IEEE European Test Symposium, 2019

2018

Efficient Realization of Householder Transform Through Algorithm-Architecture Co-Design for Acceleration of QR Factorization.

[BibT_eX]

[DOI]

IEEE Trans. Parallel Distributed Syst., 2018

Efficient Realization of Givens Rotation through Algorithm-Architecture Co-design for Acceleration of QR Factorization.

[BibT_eX]

[DOI]

CoRR, 2018

Parameterized Posit Arithmetic Hardware Generator.

[BibT_eX]

[DOI]

Proceedings of the 36th IEEE International Conference on Computer Design, 2018

Achieving Efficient Realization of Kalman Filter on CGRA Through Algorithm-Architecture Co-design.

[BibT_eX]

[DOI]

Proceedings of the Applied Reconfigurable Computing. Architectures, Tools, and Applications, 2018

2017

Accelerating BLAS and LAPACK via Efficient Floating Point Architecture Design.

[BibT_eX]

[DOI]

Parallel Process. Lett., 2017

2016

Accelerating BLAS on Custom Architecture through Algorithm-Architecture Co-design.

[BibT_eX]

[DOI]

CoRR, 2016

Achieving Efficient QR Factorization by Algorithm-Architecture Co-design of Householder Transformation.

[BibT_eX]

[DOI]

Proceedings of the 29th International Conference on VLSI Design and 15th International Conference on Embedded Systems, 2016

Efficient Realization of Table Look-Up Based Double Precision Floating Point Arithmetic.

[BibT_eX]

[DOI]

Proceedings of the 29th International Conference on VLSI Design and 15th International Conference on Embedded Systems, 2016

Enabling in-memory computation of binary BLAS using ReRAM crossbar arrays.

[BibT_eX]

[DOI]

Debjyoti Bhattacharjee

Farhad Merchant

Anupam Chattopadhyay

Proceedings of the 2016 IFIP/IEEE International Conference on Very Large Scale Integration, 2016

2015

Micro-architectural Enhancements in Distributed Memory CGRAs for LU and QR Factorizations.

[BibT_eX]

[DOI]

Proceedings of the 28th International Conference on VLSI Design, 2015

2014

A framework for post-silicon realization of arbitrary instruction extensions on reconfigurable data-paths.

[BibT_eX]

[DOI]

J. Syst. Archit., 2014

Efficient QR Decomposition Using Low Complexity Column-wise Givens Rotation (CGR).

[BibT_eX]

[DOI]

Proceedings of the 2014 27th International Conference on VLSI Design, 2014

Scalable and energy-efficient reconfigurable accelerator for column-wise givens rotation.

[BibT_eX]

[DOI]

Proceedings of the 22nd International Conference on Very Large Scale Integration, 2014

Co-exploration of NLA kernels and specification of Compute Elements in distributed memory CGRAs.

[BibT_eX]

[DOI]

Proceedings of the XIVth International Conference on Embedded Computer Systems: Architectures, 2014

Efficient and scalable CGRA-based implementation of Column-wise Givens Rotation.

[BibT_eX]

[DOI]

Proceedings of the IEEE 25th International Conference on Application-Specific Systems, 2014

2011

A Fully Pipelined Modular Multiple Precision Floating Point Multiplier with Vector Support.

[BibT_eX]

[DOI]

Alok Baluni

Farhad Merchant

S. K. Nandy

Srinivasan Balakrishnan

Proceedings of the International Symposium on Electronic System Design, 2011

Farhad Merchant

Timeline

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