Ralf Brederlow
Orcid: 0000-0002-8118-757XAffiliations:
- Technical University Munich, Germany
According to our database1,
Ralf Brederlow
authored at least 35 papers
between 2001 and 2023.
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Bibliography
2023
A FeFET In-Memory-Computing Core with Offset Cancellation for Mitigating Computational Errors.
Proceedings of the 49th IEEE European Solid State Circuits Conference, 2023
A 2.2 fA/√Hz, 120 dB Dynamic Range, 12 GΩ Hybrid Readout Interface for Various Ionic Spectroscopy Applications.
Proceedings of the 49th IEEE European Solid State Circuits Conference, 2023
Structured Design and Evaluation of a Resistor-Based PUF Robust Against PVT-Variations.
Proceedings of the 26th International Symposium on Design and Diagnostics of Electronic Circuits and Systems, 2023
Analog/Mixed-Signal Standard Cell Based Approach for Automated Circuit Generation of Neural Network Accelerators.
Proceedings of the 38th Conference on Design of Circuits and Integrated Systems, 2023
VE-FIDES: Designing Trustworthy Supply Chains Using Innovative Fingerprinting Implementations.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2023
Analysis of Acceleration Data Using Low-Power Embedded Devices to Detect Gear Faults.
Proceedings of the 19th IEEE International Conference on Automation Science and Engineering, 2023
Silicon-based CMOS Stress Sensors for Tactile Perception based Smart Skin for Prostheses.
Proceedings of the IEEE Biomedical Circuits and Systems Conference, 2023
2022
A Dynamic Charge-Transfer-Based Crossbar with Low Sensitivity to Parasitic Wire-Resistance.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2022
2021
Towards Easy-to-Use Bacteria Sensing: Modeling and Simulation of a New Environmental Impedimetric Biosensor in Fluids.
Sensors, 2021
Proceedings of the IEEE International Symposium on Circuits and Systems, 2021
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2021
2020
IEEE J. Solid State Circuits, 2020
Quantization Considerations of Dense Layers in Convolutional Neural Networks for Resistive Crossbar Implementation.
Proceedings of the 9th International Conference on Modern Circuits and Systems Technologies, 2020
2019
A CMOS Temperature Stabilized 2-Dimensional Mechanical Stress Sensor with 11-bit Resolution.
Proceedings of the 2019 Symposium on VLSI Circuits, Kyoto, Japan, June 9-14, 2019, 2019
Proceedings of the 17th IEEE International New Circuits and Systems Conference, 2019
2018
A Hysteretic Buck Converter With 92.1% Maximum Efficiency Designed for Ultra-Low Power and Fast Wake-Up SoC Applications.
IEEE J. Solid State Circuits, 2018
2017
A 92.1% efficient DC-DC converter for ultra-low power microcontrollers with fast wake-up.
Proceedings of the 2017 IEEE Custom Integrated Circuits Conference, 2017
2016
Towards Side-Channel Secure Firmware Updates - A Minimalist Anomaly Detection Approach.
Proceedings of the Foundations and Practice of Security - 9th International Symposium, 2016
2015
Session 27 overview: Physical sensors: Imagers, MEMS, medical and displays subcommittee.
Proceedings of the 2015 IEEE International Solid-State Circuits Conference, 2015
2014
Architectural and Circuit Design Techniques for Power Management of Ultra-Low-Power MCU Systems.
IEEE Trans. Very Large Scale Integr. Syst., 2014
Proceedings of the 9th Workshop on Embedded Systems Security, 2014
2012
IEEE J. Solid State Circuits, 2012
2011
Proceedings of the 37th European Solid-State Circuits Conference, 2011
2007
A Complementary Switched MOSFET Architecture for the 1/f Noise Reduction in Linear Analog CMOS ICs.
IEEE J. Solid State Circuits, 2007
Statistical analysis of systematic and random variability of flip-flop race immunity in 130nm and 90nm CMOS technologies.
Proceedings of the IFIP VLSI-SoC 2007, 2007
An Integrated Gravimetric FBAR Circuit for Operation in Liquids Using a Flip-Chip Extended 0.13μm CMOS Technology.
Proceedings of the 2007 IEEE International Solid-State Circuits Conference, 2007
2006
A low-power true random number generator using random telegraph noise of single oxide-traps.
Proceedings of the 2006 IEEE International Solid State Circuits Conference, 2006
Proceedings of the 2006 IEEE International Solid State Circuits Conference, 2006
2005
Effects of inhomogeneous negative bias temperature stress on p-channel MOSFETs of analog and RF circuits.
Microelectron. Reliab., 2005
IEEE J. Solid State Circuits, 2005
2004
Proceedings of the 33rd European Solid-State Circuits Conference, 2004
2003
IEEE J. Solid State Circuits, 2003
2001
An efficient and precise design method to optimize device areas in mismatch and flicker-noise sensitive analog circuits.
Proceedings of the 2001 8th IEEE International Conference on Electronics, 2001