Dirk J. Wouters

Orcid: 0000-0002-6766-8553

According to our database1, Dirk J. Wouters authored at least 31 papers between 2012 and 2024.

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Bibliography

2024
Improved Arithmetic Performance by Combining Stateful and Non-Stateful Logic in Resistive Random Access Memory 1T-1R Crossbars.
Adv. Intell. Syst., March, 2024

Synaptogen: A cross-domain generative device model for large-scale neuromorphic circuit design.
CoRR, 2024

2023
Sequence learning in a spiking neuronal network with memristive synapses.
Neuromorph. Comput. Eng., September, 2023

System model of neuromorphic sequence learning on a memristive crossbar array.
Neuromorph. Comput. Eng., June, 2023

Bit slicing approaches for variability aware ReRAM CIM macros.
it Inf. Technol., May, 2023

Coherent noise enables probabilistic sequence replay in spiking neuronal networks.
PLoS Comput. Biol., 2023

Demonstration of neuromorphic sequence learning on a memristive array.
Proceedings of the Neuro-Inspired Computational Elements Conference, 2023

Design Limitations in Oxide-Based Memristive Ternary Content Addressable Memories.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2023

Eliminating Capacitive Sneak Paths in Associative Capacitive Networks based on Complementary Resistive Switches for In-Memory Computing.
Proceedings of the IEEE International Memory Workshop, 2023

Work-in-Progress: A Universal Instrumentation Platform for Non-Volatile Memories.
Proceedings of the International Conference on Hardware/Software Codesign and System Synthesis, 2023

2022
Sequence learning, prediction, and replay in networks of spiking neurons.
PLoS Comput. Biol., 2022

Reliability aspects of binary vector-matrix-multiplications using ReRAM devices.
Neuromorph. Comput. Eng., 2022

MNEMOSENE: Tile Architecture and Simulator for Memristor-based Computation-in-memory.
ACM J. Emerg. Technol. Comput. Syst., 2022

A Voltage-Controlled, Oscillation-Based ADC Design for Computation-in-Memory Architectures Using Emerging ReRAMs.
ACM J. Emerg. Technol. Comput. Syst., 2022

A High Throughput Generative Vector Autoregression Model for Stochastic Synapses.
CoRR, 2022

Endurance of 2 Mbit Based BEOL Integrated ReRAM.
IEEE Access, 2022

A failure analysis framework of ReRAM In-Memory Logic operations.
Proceedings of the IEEE International Test Conference in Asia, 2022

Analysis of VMM Operations on 1S1R Crossbar Arrays and the Influence of Wire Resistances.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2022


2021
Tuning the Memory Window of TaOx ReRAM Using the RF Sputtering Power.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2021

2020
In-Memory Binary Vector-Matrix Multiplication Based on Complementary Resistive Switches.
Adv. Intell. Syst., 2020

The speed of sequence processing in biological neuronal networks.
Proceedings of the NICE '20: Neuro-inspired Computational Elements Workshop, 2020

A Mott Insulator-Based Oscillator Circuit for Reservoir Computing.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2020

2019
Memristive Device Modeling and Circuit Design Exploration for Computation-in-Memory.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2019

From Emerging Memory to Novel Devices for Neuromorphic Systems: Consequences for the Reliability Requirements of Memristive Devices.
Proceedings of the IEEE International Reliability Physics Symposium, 2019

Constraints on sequence processing speed in biological neuronal networks.
Proceedings of the International Conference on Neuromorphic Systems, 2019

2018
The influence of interfacial (sub)oxide layers on the properties of pristine resistive switching devices.
Proceedings of the Non-Volatile Memory Technology Symposium, 2018

2016
Lowering forming voltage and forming-free behavior of Ta2O5 ReRAM devices.
Proceedings of the 46th European Solid-State Device Research Conference, 2016

2015
Phase-Change and Redox-Based Resistive Switching Memories.
Proc. IEEE, 2015

Memristor based computation-in-memory architecture for data-intensive applications.
Proceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition, 2015

2012
Analysis of the effect of cell parameters on the maximum RRAM array size considering both read and write.
Proceedings of the 2012 European Solid-State Device Research Conference, 2012


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