Qing-Tai Zhao

Orcid: 0000-0002-2794-2757

According to our database1, Qing-Tai Zhao authored at least 14 papers between 2012 and 2023.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

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Bibliography

2023
High Performance 5 nm Si Nanowire FETs with a Record Small SS = 2.3 mV/dec and High Transconductance at 5.5 K Enabled by Dopant Segregated Silicide Source/Drain.
Proceedings of the 2023 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits), 2023

Comparison between WKB and Wavelet Approach for Analytical Calculation of Tunneling Currents in Schottky Barrier Field-Effect Transistors.
Proceedings of the 30th International Conference on Mixed Design of Integrated Circuits and System, 2023

2022
Experimental and Theoretical Analysis of Stateful Logic in Passive and Active Crossbar Arrays for Computation-in-Memory.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2022

GeSn Vertical Gate-all-around Nanowire n-type MOSFETs.
Proceedings of the 52nd IEEE European Solid-State Device Research Conference, 2022

Ferroelectric Schottky Barrier MOSFET as Analog Synapses for Neuromorphic Computing.
Proceedings of the 48th IEEE European Solid State Circuits Conference, 2022


2021
4-Terminal Ferroelectric Schottky Barrier Field Effect Transistors as Artificial Synapses.
Proceedings of the 51st IEEE European Solid-State Device Research Conference, 2021

2017
Experimental characterization of the static noise margins of strained silicon complementary tunnel-FET SRAM.
Proceedings of the 47th European Solid-State Device Research Conference, 2017

Ultrathin lateral unidirectional bipolar-type insulated-gate transistor as pH sensor.
Proceedings of the 47th European Solid-State Device Research Conference, 2017

2016
Si n-TFETs on ultra thin body with suppressed ambipolarity.
Proceedings of the 46th European Solid-State Device Research Conference, 2016

Implementation of a DC compact model for double-gate Tunnel-FET based on 2D calculations and application in circuit simulation.
Proceedings of the 46th European Solid-State Device Research Conference, 2016

2014
Experimental demonstration of improved analog device performance in GAA-NW-TFETs.
Proceedings of the 44th European Solid State Device Research Conference, 2014

2013
Low frequency noise in strained silicon nanowire array MOSFETs and Tunnel-FETs.
Proceedings of the European Solid-State Device Research Conference, 2013

2012
Si tunneling transistors with high on-currents and slopes of 50 mV/dec using segregation doped Nisi2 tunnel junctions.
Proceedings of the 2012 European Solid-State Device Research Conference, 2012


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