Satoru Tanoi

According to our database1, Satoru Tanoi authored at least 11 papers between 1994 and 2024.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Dataset
Other 

Links

On csauthors.net:

Bibliography

2024
A 20Gb/s QPSK Receiver with Mixed-Signal Carrier, Timing, and Data Recovery Using 3-bit ADCs.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2024

2021

2014
A High Output Resistance 1.2-V VDD Current Mirror with Deep Submicron Vertical MOSFETs.
IEICE Trans. Electron., 2014

2012
A Ring-VCO-Based Injection-Locked Frequency Multiplier with Novel Pulse Generation Technique in 65 nm CMOS.
IEICE Trans. Electron., 2012

Injection-locked fractional frequency multiplier with automatic reference pulse-selection technique.
IEICE Electron. Express, 2012

2011
A ring-VCO-based injection-locked frequency multiplier using a new pulse generation technique in 65 nm CMOS.
Proceedings of the International SoC Design Conference, 2011

2005
RF-CMOS Implementation of UWB Transceivers and Its Application to Video Transmission.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2005

1998
BIST: required for embedded DRAM.
Proceedings of the Proceedings IEEE International Test Conference 1998, 1998

1997
On-wafer BIST of a 200-Gb/s failed-bit search for 1-Gb DRAM.
IEEE J. Solid State Circuits, 1997

1996
A 250-622 MHz deskew and jitter-suppressed clock buffer using two-loop architecture.
IEEE J. Solid State Circuits, 1996

1994
A 32-bank 256-Mb DRAM with cache and TAG.
IEEE J. Solid State Circuits, November, 1994


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