Kaustav Banerjee
Orcid: 0000-0001-5344-0921Affiliations:
- University of California, Santa Barbara, CA, USA
According to our database1,
Kaustav Banerjee
authored at least 70 papers
between 1999 and 2023.
Collaborative distances:
Collaborative distances:
Awards
IEEE Fellow
IEEE Fellow 2012, "For contributions to modeling and design of nanoscale integrated circuit interconnects".
Timeline
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Online presence:
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on orcid.org
On csauthors.net:
Bibliography
2023
Proceedings of the Device Research Conference, 2023
2020
Correction to "Analytical Thermal Model for Self-Heating in Advanced FinFET Devices With Implications for Design and Reliability".
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020
2013
Analytical Thermal Model for Self-Heating in Advanced FinFET Devices With Implications for Design and Reliability.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2013
Proceedings of the European Solid-State Device Research Conference, 2013
2012
Fast High-Frequency Impedance Extraction of Horizontal Interconnects and Inductors in 3-D ICs With Multiple Substrates.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2012
2010
A Novel Variation-Tolerant Keeper Architecture for High-Performance Low-Power Wide Fan-In Dynamic or Gates.
IEEE Trans. Very Large Scale Integr. Syst., 2010
Corrections to "Analytical Expressions for High-Frequency VLSI Interconnect Impedance Extraction in the Presence of a Multilayer Conductive Substrate" [Jul 09 1047-1060].
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2010
IEEE Des. Test Comput., 2010
A new paradigm in the design of energy-efficient digital circuits using laterally-actuated double-gate NEMs.
Proceedings of the 2010 International Symposium on Low Power Electronics and Design, 2010
Work-function variation induced fluctuation in bias-temperature-instability characteristics of emerging metal-gate devices and implications for digital design.
Proceedings of the 2010 International Conference on Computer-Aided Design, 2010
Efficient 3D high-frequency impedance extraction for general interconnects and inductors above a layered substrate.
Proceedings of the Design, Automation and Test in Europe, 2010
Aging-resilient design of pipelined architectures using novel detection and correction circuits.
Proceedings of the Design, Automation and Test in Europe, 2010
Design and analysis of compact ultra energy-efficient logic gates using laterally-actuated double-electrode NEMS.
Proceedings of the 47th Design Automation Conference, 2010
2009
Analytical Expressions for High-Frequency VLSI Interconnect Impedance Extraction in the Presence of a Multilayer Conductive Substrate.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2009
IET Comput. Digit. Tech., 2009
Proceedings of the 11th International Workshop on System-Level Interconnect Prediction (SLIP 2009), 2009
Proceedings of the 2009 International Symposium on Physical Design, 2009
Fast 3-D thermal analysis of complex interconnect structures using electrical modeling and simulation methodologies.
Proceedings of the 2009 International Conference on Computer-Aided Design, 2009
Variability analysis of FinFET-based devices and circuits considering electrical confinement and width quantization.
Proceedings of the 2009 International Conference on Computer-Aided Design, 2009
Proceedings of the ACM/SIGDA 17th International Symposium on Field Programmable Gate Arrays, 2009
Proceedings of the 14th Asia South Pacific Design Automation Conference, 2009
2008
A Design-Specific and Thermally-Aware Methodology for Trading-Off Power and Performance in Leakage-Dominant CMOS Technologies.
IEEE Trans. Very Large Scale Integr. Syst., 2008
Statistical modeling of metal-gate work-function variability in emerging device technologies and implications for circuit design.
Proceedings of the 2008 International Conference on Computer-Aided Design, 2008
High-Frequency Mutual Impedance Extraction of VLSI Interconnects In the Presence of a Multi-layer Conducting Substrate.
Proceedings of the Design, Automation and Test in Europe, 2008
Analysis and implications of parasitic and screening effects on the high-frequency/RF performance of tunneling-carbon nanotube FETs.
Proceedings of the 45th Design Automation Conference, 2008
2007
Tutorial 5: SoC Communication Architectures: Technology, Current Practice, Research, and Trends.
Proceedings of the 20th International Conference on VLSI Design (VLSI Design 2007), 2007
Proceedings of the 44th Design Automation Conference, 2007
2006
Proceedings of the 1st International ICST Conference on Nano-Networks, 2006
Proceedings of the 7th International Symposium on Quality of Electronic Design (ISQED 2006), 2006
An electrothermally-aware full-chip substrate temperature gradient evaluation methodology for leakage dominant technologies with implications for power estimation and hot-spot management.
Proceedings of the 2006 International Conference on Computer-Aided Design, 2006
A thermally-aware performance analysis of vertically integrated (3-D) processor-memory hierarchy.
Proceedings of the 43rd Design Automation Conference, 2006
Proceedings of the 43rd Design Automation Conference, 2006
Proceedings of the 43rd Design Automation Conference, 2006
Proceedings of the 12th International Conference on Architectural Support for Programming Languages and Operating Systems, 2006
Electrothermal engineering in the nanometer era: from devices and interconnects to circuits and systems.
Proceedings of the 2006 Conference on Asia South Pacific Design Automation: ASP-DAC 2006, 2006
2005
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2005
Modeling and analysis of nonuniform substrate temperature effects on global ULSI interconnects.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2005
Impact of On-chip Inductance on Power Distribution Network Design for Nanometer Scale Integrated Circuits.
Proceedings of the 6th International Symposium on Quality of Electronic Design (ISQED 2005), 2005
Proceedings of the 6th International Symposium on Quality of Electronic Design (ISQED 2005), 2005
A probabilistic framework for power-optimal repeater insertion in global interconnects under parameter variations.
Proceedings of the 2005 International Symposium on Low Power Electronics and Design, 2005
A Thermally-Aware Methodology for Design-Specific Optimization of Supply and Threshold Voltages in Nanometer Scale ICs.
Proceedings of the 23rd International Conference on Computer Design (ICCD 2005), 2005
Proceedings of the 2005 International Conference on Computer-Aided Design, 2005
2004
Modeling techniques and verification methodologies for substrate coupling effects in mixed-signal system-on-chip designs.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2004
Proceedings of the 5th International Symposium on Quality of Electronic Design (ISQED 2004), 2004
Proceedings of the 5th International Symposium on Quality of Electronic Design (ISQED 2004), 2004
A probabilistic framework to estimate full-chips subthreshold leakage power distribution considering within-die and die-to-die P-T-V variations.
Proceedings of the 2004 International Symposium on Low Power Electronics and Design, 2004
Simultaneous optimization of supply and threshold voltages for low-power and high-performance circuits in the leakage dominant era.
Proceedings of the 41th Design Automation Conference, 2004
2003
Proceedings of the 2003 International Conference on Computer-Aided Design, 2003
Nano, quantum, and molecular computing: are we ready for the validation and test challenges?
Proceedings of the Eighth IEEE International High-Level Design Validation and Test Workshop 2003, 2003
2002
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2002
Modeling and Design of a Low-Voltage SOI Suspended-Gate MOSFET (SG-MOSFET) with a Metal-over-Gate Architecture.
Proceedings of the 3rd International Symposium on Quality of Electronic Design, 2002
Proceedings of the 3rd International Symposium on Quality of Electronic Design, 2002
Proceedings of the 2002 International Symposium on Circuits and Systems, 2002
Analysis and optimization of substrate noise coupling in single-chip RF transceiver design.
Proceedings of the 2002 IEEE/ACM International Conference on Computer-aided Design, 2002
Proceedings of the 39th Design Automation Conference, 2002
2001
Proc. IEEE, 2001
3-D ICs: a novel chip design for improving deep-submicrometer interconnect performance and systems-on-chip integration.
Proc. IEEE, 2001
Proceedings of the 2nd International Symposium on Quality of Electronic Design (ISQED 2001), 2001
Proceedings of the 2001 International Symposium on Physical Design, 2001
Compact Modeling and SPICE-Based Simulation for Electrothermal Analysis of Multilevel ULSI Interconnects.
Proceedings of the 2001 IEEE/ACM International Conference on Computer-Aided Design, 2001
Coupled Analysis of Electromigration Reliability and Performance in ULSI Signal Nets.
Proceedings of the 2001 IEEE/ACM International Conference on Computer-Aided Design, 2001
Proceedings of the 2001 IEEE/ACM International Conference on Computer-Aided Design, 2001
Analysis of On-Chip Inductance Effects using a Novel Performance Optimization Methodology for Distributed RLC Interconnects.
Proceedings of the 38th Design Automation Conference, 2001
Analysis of Non-Uniform Temperature-Dependent Interconnect Performance in High Performance ICs.
Proceedings of the 38th Design Automation Conference, 2001
A fast analytical technique for estimating the bounds of on-chip clock wire inductance.
Proceedings of the IEEE 2001 Custom Integrated Circuits Conference, 2001
Effects of non-uniform substrate temperature on the clock signal integrity in high performance designs.
Proceedings of the IEEE 2001 Custom Integrated Circuits Conference, 2001
2000
Proceedings of the Second IEEE/ACM International Workshop on System-Level Interconnect Prediction (SLIP 2000), 2000
Proceedings of the 37th Conference on Design Automation, 2000
1999
Proceedings of the 36th Conference on Design Automation, 1999