Jiann-Shiun Yuan

Orcid: 0000-0002-2548-8327

Affiliations:
  • University of Central Florida, Department of Electrical and Computer Engineering, Orlando, USA


According to our database1, Jiann-Shiun Yuan authored at least 65 papers between 1991 and 2024.

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Bibliography

2024
Impacting Robustness in Deep Learning-Based NIDS through Poisoning Attacks.
Algorithms, April, 2024

Functional microRNA-targeting drug discovery by graph-based deep learning.
Patterns, January, 2024

Self-Supervised Graph Transformer for Deepfake Detection.
IEEE Access, 2024

2023
ProtEC: A Transformer Based Deep Learning System for Accurate Annotation of Enzyme Commission Numbers.
IEEE ACM Trans. Comput. Biol. Bioinform., 2023

2022
AMPDeep: hemolytic activity prediction of antimicrobial peptides using transfer learning.
BMC Bioinform., December, 2022

MolData, a molecular benchmark for disease and target based machine learning.
J. Cheminformatics, 2022

Mitigation of Black-Box Attacks on Intrusion Detection Systems-Based ML.
Comput., 2022

2021
Resilient and Secure Hardware Devices Using ASL.
ACM J. Emerg. Technol. Comput. Syst., 2021

ADD: Attention-Based DeepFake Detection Approach.
Big Data Cogn. Comput., 2021

2020
Strong Logic Obfuscation with Low Overhead against IC Reverse Engineering Attacks.
ACM Trans. Design Autom. Electr. Syst., 2020

A scalable and reconfigurable in-memory architecture for ternary deep spiking neural network with ReRAM based neurons.
Neurocomputing, 2020

Artificial Intelligence for COVID-19 Drug Discovery and Vaccine Development.
Frontiers Artif. Intell., 2020

Developing a Robust Defensive System against Adversarial Examples Using Generative Adversarial Networks.
Big Data Cogn. Comput., 2020

TranScreen: Transfer Learning on Graph-Based Anti-Cancer Virtual Screening Model.
Big Data Cogn. Comput., 2020

Substrate Bias Effect on Dynamic Characteristics of a Monolithically Integrated GaN Half-Bridge.
Proceedings of the 2020 IEEE International Reliability Physics Symposium, 2020

ESD Robustness of GaN-on-Si Power Devices under Substrate Biases by means of TLP/VFTLP Tests.
Proceedings of the 2020 IEEE International Reliability Physics Symposium, 2020

2019
Utilizing Transfer Learning and Homomorphic Encryption in a Privacy Preserving and Secure Biometric Recognition System.
Comput., 2019

RazorNet: Adversarial Training and Noise Training on a Deep Neural Network Fooled by a Shallow Neural Network.
Big Data Cogn. Comput., 2019

Low-Side GaN Power Device Dynamic Ron Characteristics Under Different Substrate Biases.
Proceedings of the IEEE International Reliability Physics Symposium, 2019

Noise Injection Adaption: End-to-End ReRAM Crossbar Non-ideal Effect Adaption for Neural Network Mapping.
Proceedings of the 56th Annual Design Automation Conference 2019, 2019

2018
Analysis and Simulation of Capacitor-Less ReRAM-Based Stochastic Neurons for the in-Memory Spiking Neural Network.
IEEE Trans. Biomed. Circuits Syst., 2018

Leveraging Image Representation of Network Traffic Data and Transfer Learning in Botnet Detection.
Big Data Cogn. Comput., 2018

An Experimental Evaluation of Fault Diagnosis from Imbalanced and Incomplete Data for Smart Semiconductor Manufacturing.
Big Data Cogn. Comput., 2018

Anomaly Generation Using Generative Adversarial Networks in Host-Based Intrusion Detection.
Proceedings of the 9th IEEE Annual Ubiquitous Computing, 2018

Resilient AES Against Side-Channel Attack Using All-Spin Logic.
Proceedings of the 2018 on Great Lakes Symposium on VLSI, 2018

ECG Arrhythmia Classification Using Transfer Learning from 2- Dimensional Deep CNN Features.
Proceedings of the 2018 IEEE Biomedical Circuits and Systems Conference, 2018

2017
Tunnel FET Current Mode Logic for DPA-Resilient Circuit Designs.
IEEE Trans. Emerg. Top. Comput., 2017

A 12-Bit Ultra-Low Voltage Noise Shaping Successive-Approximation Register Analogto-Digital Converter Using Emerging TFETs.
J. Low Power Electron., 2017

Security Protection for Magnetic Tunnel Junction.
CoRR, 2017

Security Analysis of Tunnel Field-Effect Transistor for Low Power Hardware.
CoRR, 2017

Logic Obfuscation against IC Reverse Engineering Attacks Using PLGs.
Proceedings of the 2017 IEEE International Conference on Computer Design, 2017

Leveraging All-Spin Logic to Improve Hardware Security.
Proceedings of the on Great Lakes Symposium on VLSI 2017, 2017

Security analysis of computing systems from circuit-architectural perspective.
Proceedings of the IEEE Conference on Dependable and Secure Computing, 2017

Capacitor-less RRAM-based stochastic neuron for event-based unsupervised learning.
Proceedings of the IEEE Biomedical Circuits and Systems Conference, 2017

2016
Ultra-Low Power Successive Approximation Analog-to-Digital Converter Using Emerging Tunnel Field Effect Transistor Technology.
J. Low Power Electron., 2016

Emerging Technology-Based Design of Primitives for Hardware Security.
ACM J. Emerg. Technol. Comput. Syst., 2016

Leverage Emerging Technologies For DPA-Resilient Block Cipher Design.
Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition, 2016

2015
Process and temperature robust voltage multiplier design for RF energy harvesting.
Microelectron. Reliab., 2015

2014
Leveraging Emerging Technology for Hardware Security - Case Study on Silicon Nanowire FETs and Graphene SymFETs.
Proceedings of the 23rd IEEE Asian Test Symposium, 2014

2013
Experimental evaluation of hot electron reliability on differential Clapp-VCO.
Microelectron. Reliab., 2013

2012
RF stress effects on CMOS LC-loaded VCO reliability evaluated by experiments.
Microelectron. Reliab., 2012

Examination of hot carrier effects of the AlGaAs/InGaAs pHEMT through device simulation.
Microelectron. Reliab., 2012

2011
NBTI reliability on high-k metal-gate SiGe transistor and circuit performances.
Microelectron. Reliab., 2011

Thermal reliability of VCO using InGaP/GaAs HBTs.
Microelectron. Reliab., 2011

Evaluation of gate oxide breakdown effect on cascode class E power amplifier performance.
Microelectron. Reliab., 2011

2010
Design of Asynchronous Circuits for High Soft Error Tolerance in Deep Submicrometer CMOS Circuits.
IEEE Trans. Very Large Scale Integr. Syst., 2010

Impact of strain on hot electron reliability of dual-band power amplifier and integrated LNA-mixer RF performances.
Microelectron. Reliab., 2010

Voltage stress effect on class AB power amplifier and mixed-signal sample-hold circuit.
Microelectron. Reliab., 2010

Electro-thermal stress effect on InGaP/GaAs heterojunction bipolar low-noise amplifier performance.
Microelectron. Reliab., 2010

2008
InGaP/GaAs heterojunction bipolar transistor and RF power amplifier reliability.
Microelectron. Reliab., 2008

PMOS breakdown effects on digital circuits - Modeling and analysis.
Microelectron. Reliab., 2008

2006
Study of performance degradations in DC-DC converter due to hot carrier stress by simulation.
Microelectron. Reliab., 2006

Energy-Aware Dual-Rail Bit-Wise Completion Pipelined Arithmetic Circuit Design.
J. Low Power Electron., 2006

Improving power-awareness of pipelined array multipliers using two-dimensional pipeline gating and its application on FIR design.
Integr., 2006

2005
Teaching low-power electronic design in electrical and computer engineering.
IEEE Trans. Educ., 2005

Dynamic Active-bit Detection and Operands Exchange for Designing Energy-aware Asynchronous Multipliers.
Proceedings of the 2005 International Conference on Computer Design, 2005

2004
Teaching asynchronous design in digital integrated circuits.
IEEE Trans. Educ., 2004

Optimization of NULL convention self-timed circuits.
Integr., 2004

2003
High Throughput Power-Aware FIR Filter Design Based on Fine-Grain Pipelining Multipliers and Adders.
Proceedings of the 2003 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2003), 2003

Power-aware pipelined multiplier design based on 2-dimensional pipeline gating.
Proceedings of the 13th ACM Great Lakes Symposium on VLSI 2003, 2003

2002
NULL convention multiply and accumulate unit with conditional rounding, scaling, and saturation.
J. Syst. Archit., 2002

2001
Delay-insensitive gate-level pipelining.
Integr., 2001

2000
Overview of SiGe Technology Modeling and Application.
Proceedings of the 1st International Symposium on Quality of Electronic Design (ISQED 2000), 2000

1991
Testing the impact of process defects on ECL power-delay performance.
Proceedings of the 9th IEEE VLSI Test Symposium (VTS'91), 1991

Statistical sensitivity simulation for integrating design and testing of MOSFET integrated circuits.
Proceedings of the 9th IEEE VLSI Test Symposium (VTS'91), 1991


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