Peiyi Zhao

Orcid: 0000-0001-5461-9632

According to our database1, Peiyi Zhao authored at least 24 papers between 2000 and 2023.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

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PhD thesis 
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Links

On csauthors.net:

Bibliography

2023
Low-Power Redundant-Transition-Free TSPC Dual-Edge-Triggering Flip-Flop Using Single-Transistor-Clocked Buffer.
IEEE Trans. Very Large Scale Integr. Syst., May, 2023

Exploring How to Improve User Experience of Enterprise Service Products through "Dual Perspective Model".
Proceedings of the Design, User Experience, and Usability, 2023

2022
Design of Non-uniform Constellations in the Channel with Phase Noise.
Proceedings of the 2022 International Wireless Communications and Mobile Computing, 2022

On Bit Mapping for Golden Angle Modulation in the Presence of Strong Phase Noise.
Proceedings of the IEEE International Symposium on Broadband Multimedia Systems and Broadcasting, 2022

2021
Low-Energy Acceleration of Binarized Convolutional Neural Networks Using a Spin Hall Effect Based Logic-in-Memory Architecture.
IEEE Trans. Emerg. Top. Comput., 2021

Ultra-low-voltage Low-power Self-adaptive Static Pulsed Latch.
Proceedings of the 14th IEEE International Conference on ASIC, 2021

2018
Fast Adjustable NPN Classification using Generalized Symmetries.
Proceedings of the 28th International Conference on Field Programmable Logic and Applications, 2018

2013
A clocked differential switch logic using floating-gate MOS transistors.
Proceedings of the IEEE 10th International Conference on ASIC, 2013

2011
Design of Sequential Elements for Low Power Clocking System.
IEEE Trans. Very Large Scale Integr. Syst., 2011

2010
PMCNOC: A Pipelining Multi-channel Central Caching Network-on-chip Communication Architecture Design.
J. Signal Process. Syst., 2010

Design of Asynchronous Circuits for High Soft Error Tolerance in Deep Submicrometer CMOS Circuits.
IEEE Trans. Very Large Scale Integr. Syst., 2010

2009
Low-Power Clocked-Pseudo-NMOS Flip-Flop for Level Conversion in Dual Supply Systems.
IEEE Trans. Very Large Scale Integr. Syst., 2009

Incorporating real world integrated circuit in a liberal arts computer science program.
Proceedings of the IEEE International Conference on Microelectronic Systems Education, 2009

2008
Power analysis of the Huffman decoding tree.
Proceedings of the International Conference on Image Processing, 2008

2007
Low-Power Clock Branch Sharing Double-Edge Triggered Flip-Flop.
IEEE Trans. Very Large Scale Integr. Syst., 2007

PMCNOC: A Pipelining Multi-Channel Central Caching Network-on-Chip Communication Architecture Design.
Proceedings of the IEEE Workshop on Signal Processing Systems, 2007

A Low Power Domino with Differential-Controlled-Keeper.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2007), 2007

Soft Error Hardening for Asynchronous Circuits.
Proceedings of the 22nd IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2007), 2007

2006
A low-power clock frequency multiplier.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006

2004
High-performance and low-power conditional discharge flip-flop.
IEEE Trans. Very Large Scale Integr. Syst., 2004

A Double-Edge Implicit-Pulsed Level Convert Flip-Flop.
Proceedings of the 2004 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2004), 2004

Contention reduced/conditional discharge flip-flops for level conversion in CVS systems.
Proceedings of the 2004 International Symposium on Circuits and Systems, 2004

2003
Low Power Conditional-Discharge Pulsed Flip-Flops.
Proceedings of the International Conference on Embedded Systems and Applications, 2003

2000
On the isomorphism of expressions.
Inf. Process. Lett., 2000


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