Xiao Peng

Affiliations:
  • Waseda University, Graduate School of Information, Production and Systems, Japan


According to our database1, Xiao Peng authored at least 19 papers between 2010 and 2014.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

Legend:

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Links

On csauthors.net:

Bibliography

2014
Dynamic Check Message Majority-Logic Decoding Algorithm for Non-binary LDPC Codes.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2014

2013
A 5.83pJ/bit/iteration High-Parallel Performance-Aware LDPC Decoder IP Core Design for WiMAX in 65nm CMOS.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2013

A Dual-Mode Deblocking Filter Design for HEVC and H.264/AVC.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2013

High-parallel performance-aware LDPC decoder IP core design for WiMAX.
Proceedings of the IEEE 56th International Midwest Symposium on Circuits and Systems, 2013

A 6.72-Gb/s, 8pJ/bit/iteration WPAN LDPC decoder in 65nm CMOS.
Proceedings of the 18th Asia and South Pacific Design Automation Conference, 2013

2012
DVB-T2 LDPC Decoder with Perfect Conflict Resolution.
IPSJ Trans. Syst. LSI Des. Methodol., 2012

A 115 mW 1 Gbps Bit-Serial Layered LDPC Decoder for WiMAX.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2012

De-blocking Filter Design for HEVC and H.264/AVC.
Proceedings of the Advances in Multimedia Information Processing - PCM 2012, 2012

Distributed punctured LDPC coding scheme using novel shuffled decoding for MIMO relay channels.
Proceedings of the 20th European Signal Processing Conference, 2012

2011
A 6.72-Gb/s 8 pJ/bit/iteration IEEE 802.15.3c LDPC Decoder Chip.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2011

Ultra low power QC-LDPC decoder with high parallelism.
Proceedings of the IEEE 24th International SoC Conference, SOCC 2011, Taipei, Taiwan, 2011

A high parallel macro block level layered LDPC decoding architecture based on dedicated matrix reordering.
Proceedings of the IEEE Workshop on Signal Processing Systems, 2011

A 115mW 1Gbps QC-LDPC decoder ASIC for WiMAX in 65nm CMOS.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2011

High-parallel LDPC decoder with power gating design.
Proceedings of the 2011 IEEE 9th International Conference on ASIC, 2011

2010
A High Parallelism LDPC Decoder with an Early Stopping Criterion for WiMax and WiFi Application.
IPSJ Trans. Syst. LSI Des. Methodol., 2010

Generic Permutation Network for QC-LDPC Decoder.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2010

Permutation Network for Reconfigurable LDPC Decoder Based on Banyan Network.
IEICE Trans. Electron., 2010

An early stopping criterion for decoding LDPC codes in WiMAX and WiFi standards.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2010), May 30, 2010

High parallel variation Banyan network based permutation network for reconfigurable LDPC decoder.
Proceedings of the 21st IEEE International Conference on Application-specific Systems Architectures and Processors, 2010


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