Simone Casale Brunet

Orcid: 0000-0001-7840-1398

Affiliations:
  • École Polytechnique Fédérale de Lausanne, Switzerland


According to our database1, Simone Casale Brunet authored at least 58 papers between 2012 and 2024.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

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Bibliography

2024
Efficient Neural Clustering and Compression of Strings Through Approximate Euclidean Embeddings of the Levenshtein Distance.
Proceedings of the Data Compression Conference, 2024

2023
Design Space Exploration for Partitioning Dataflow Program on CPU-GPU Heterogeneous System.
J. Signal Process. Syst., October, 2023

Secure-by-design smart contract based on dataflow implementations.
CoRR, 2023

Exploring the data of blockchain-based metaverses.
Proceedings of the IEEE International Conference on Metaverse Computing, 2023

Unveiling social aggregation in the Decentraland metaverse platform.
Proceedings of the 2023 ACM Conference on Information Technology for Social Good, 2023

2022
The impact of NFT profile pictures within social network communities.
Proceedings of the GoodIT 2022: ACM International Conference on Information Technology for Social Good, Limassol, Cyprus, September 7, 2022

MPEG-G Reference-Based Compression of Unaligned Reads Through Ultra-Fast Alignments.
Proceedings of the Data Compression Conference, 2022

A Benchmark of Entropy Coders for the Compression of Genome Sequencing Data.
Proceedings of the Data Compression Conference, 2022

2021
Methodologies for Synthesizing and Analyzing Dynamic Dataflow Programs in Heterogeneous Systems for Edge Computing.
IEEE Open J. Circuits Syst., 2021

Performance Estimation of High-Level Dataflow Program on Heterogeneous Platforms.
Proceedings of the 14th IEEE International Symposium on Embedded Multicore/Many-core Systems-on-Chip, 2021

SIMD Parallel Execution on GPU from High-Level Dataflow Synthesis.
Proceedings of the 14th IEEE International Symposium on Embedded Multicore/Many-core Systems-on-Chip, 2021

Networks of Ethereum Non-Fungible Tokens: A graph-based analysis of the ERC-721 ecosystem.
Proceedings of the 2021 IEEE International Conference on Blockchain, 2021

Inter-actions parallel execution on GPU from high-level dataflow synthesis.
Proceedings of the 55th Asilomar Conference on Signals, Systems, and Computers, 2021

2020
Pipeline Synthesis and Optimization from Branched Feedback Dataflow Programs.
J. Signal Process. Syst., 2020

2019
An Heterogeneous Compiler of Dataflow Programs for Zynq Platforms.
Proceedings of the IEEE International Conference on Acoustics, 2019

2018
High-Precision Performance Estimation for the Design Space Exploration of Dynamic Dataflow Programs.
IEEE Trans. Multi Scale Comput. Syst., 2018

Execution Trace Graph of Dataflow Process Networks.
IEEE Trans. Multi Scale Comput. Syst., 2018

Efficient Dynamic Optimisation Heuristics for Dataflow Pipelines.
Proceedings of the 2018 IEEE International Workshop on Signal Processing Systems, 2018

Shared-variable Synchronization Approaches for Dynamic Data Flow Programs.
Proceedings of the 2018 IEEE International Workshop on Signal Processing Systems, 2018

Towards in the Field Fast Pathogens Detection Using FPGAs.
Proceedings of the 28th International Conference on Field Programmable Logic and Applications, 2018

2017
Clock-Gating of Streaming Applications for Energy Efficient Implementations on FPGAs.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2017

Design space exploration of dataflow-based Smith-Waterman FPGA implementations.
Proceedings of the 2017 IEEE International Workshop on Signal Processing Systems, 2017

High level synthesis of Smith-Waterman dataflow implementations.
Proceedings of the 2017 IEEE International Conference on Acoustics, 2017

Buffer dimensioning for throughput improvement of dynamic dataflow signal processing applications on multi-core platforms.
Proceedings of the 25th European Signal Processing Conference, 2017

Profiling of dynamic dataflow programs on MPSoC multi-core architectures.
Proceedings of the 51st Asilomar Conference on Signals, Systems, and Computers, 2017

Execution trace graph based interface synthesis of signal processing dataflow programs for heterogeneous MPSoCs.
Proceedings of the 51st Asilomar Conference on Signals, Systems, and Computers, 2017

2016
Automated Design Flow for Multi-Functional Dataflow-Based Platforms.
J. Signal Process. Syst., 2016

Dataflow Programs Analysis and Optimization Using Model Predictive Control Techniques - Two Examples of Bounded Buffer Scheduling: Deadlock Avoidance and Deadlock Recovery Strategies.
J. Signal Process. Syst., 2016

High-level synthesis of dynamic dataflow programs on heterogeneous MPSoC platforms.
Proceedings of the International Conference on Embedded Computer Systems: Architectures, 2016

Performance estimation of program partitions on multi-core platforms.
Proceedings of the 26th International Workshop on Power and Timing Modeling, 2016

High-Precision Performance Estimation of Dynamic Dataflow Programs.
Proceedings of the 10th IEEE International Symposium on Embedded Multicore/Many-core Systems-on-Chip, 2016

Programming Models and Methods for Heterogeneous Parallel Embedded Systems.
Proceedings of the 10th IEEE International Symposium on Embedded Multicore/Many-core Systems-on-Chip, 2016

A Partition Scheduler Model for Dynamic Dataflow Programs.
Proceedings of the International Conference on Computational Science 2016, 2016

Trace-based manycore partitioning of stream-processing applications.
Proceedings of the 50th Asilomar Conference on Signals, Systems and Computers, 2016

High-level system synthesis and optimization of dataflow programs for MPSoCs.
Proceedings of the 50th Asilomar Conference on Signals, Systems and Computers, 2016

2015
Execution Trace Graph Based Multi-criteria Partitioning of Stream Programs.
Proceedings of the International Conference on Computational Science, 2015

2014
Dataflow programs analysis and optimization using model predictive control techniques: An example of bounded buffer scheduling.
Proceedings of the 2014 IEEE Workshop on Signal Processing Systems, 2014

Automated design flow for coarse-grained reconfigurable platforms: An RVC-CAL multi-standard decoder use-case.
Proceedings of the XIVth International Conference on Embedded Computer Systems: Architectures, 2014

Characterizing communication behavior of dataflow programs using trace analysis.
Proceedings of the XIVth International Conference on Embedded Computer Systems: Architectures, 2014

Exploring MPEG HEVC decoder parallelism for the efficient porting onto many-core platforms.
Proceedings of the 2014 IEEE International Conference on Image Processing, 2014

A methodology for optimizing buffer sizes of dynamic dataflow fpgas implementations.
Proceedings of the IEEE International Conference on Acoustics, 2014

TURNUS: An open-source design space exploration framework for dynamic stream programs.
Proceedings of the 2014 Conference on Design and Architectures for Signal and Image Processing, 2014

Execution trace graph analysis of dataflow programs: Bounded buffer scheduling and deadlock recovery using model predictive control.
Proceedings of the 2014 Conference on Design and Architectures for Signal and Image Processing, 2014

Dataflow machines.
Proceedings of the 48th Asilomar Conference on Signals, Systems and Computers, 2014

2013
Methods to explore design space for MPEG RMC codec specifications.
Signal Process. Image Commun., 2013

Partitioning and optimization of high level stream applications for multi clock domain architectures.
Proceedings of the IEEE Workshop on Signal Processing Systems, 2013

Buffer optimization based on critical path analysis of a dataflow program design.
Proceedings of the 2013 IEEE International Symposium on Circuits and Systems (ISCAS2013), 2013

TURNUS: A design exploration framework for dataflow system design.
Proceedings of the 2013 IEEE International Symposium on Circuits and Systems (ISCAS2013), 2013

Design space exploration of high level stream programs on parallel architectures: A focus on the buffer size minimization and optimization problem.
Proceedings of the 8th International Symposium on Image and Signal Processing and Analysis, 2013

A Lego Mindstorms NXT experiment for Model Predictive Control education.
Proceedings of the 12th European Control Conference, 2013

Dataflow program analysis and refactoring techniques for design space exploration: MPEG-4 AVC/H.264 decoder implementation case study.
Proceedings of the 2013 Conference on Design and Architectures for Signal and Image Processing, 2013

Design space exploration and implementation of RVC-CAL applications using the TURNUS framework.
Proceedings of the 2013 Conference on Design and Architectures for Signal and Image Processing, 2013

Turnus: A unified dataflow design space exploration framework for heterogeneous parallel systems.
Proceedings of the 2013 Conference on Design and Architectures for Signal and Image Processing, 2013

Representing Guard Dependencies in Dataflow Execution Traces.
Proceedings of the Fifth International Conference on Computational Intelligence, 2013

Systems design space exploration by serial dataflow program execution.
Proceedings of the 2013 Asilomar Conference on Signals, 2013

Multi-clock domain optimization for reconfigurable architectures in high-level dataflow applications.
Proceedings of the 2013 Asilomar Conference on Signals, 2013

2012
Profiling of Dataflow Programs Using Post Mortem Causation Traces.
Proceedings of the 2012 IEEE Workshop on Signal Processing Systems, 2012

Design space exploration strategies for FPGA implementation of signal processing systems using CAL dataflow program.
Proceedings of the 2012 Conference on Design and Architectures for Signal and Image Processing, 2012


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