Maria J. Avedillo

Corentin Delacour

Aida Todri-Sanial

IEEE J. Emerg. Sel. Topics Circuits Syst., December, 2023

Effect of Device Mismatches in Differential Oscillatory Neural Networks.

[BibT_eX]

[DOI]

Jafar Shamsi

Teresa Serrano-Gotarredona

IEEE Trans. Circuits Syst. I Regul. Pap., February, 2023

Exploitation of Subharmonic Injection Locking for Solving Combinatorial Optimization Problems with Coupled Oscillators using VO2 based devices.

[BibT_eX]

[DOI]

Proceedings of the 19th International Conference on Synthesis, 2023

2022

How Frequency Injection Locking Can Train Oscillatory Neural Networks to Compute in Phase.

[BibT_eX]

[DOI]

IEEE Trans. Neural Networks Learn. Syst., 2022

Oscillatory Neural Networks for Obstacle Avoidance on Mobile Surveillance Robot E4.

[BibT_eX]

[DOI]

Aida Todri-Sanial

Proceedings of the International Joint Conference on Neural Networks, 2022

Mitigating the Impact of Variability in NCFET-based Coupled-Oscillator Networks Applications.

[BibT_eX]

[DOI]

Proceedings of the 29th IEEE International Conference on Electronics, Circuits and Systems, 2022

Enhancing Storage Capabilities of Oscillatory Neural Networks as Associative Memory.

[BibT_eX]

[DOI]

Proceedings of the 37th Conference on Design of Circuits and Integrated Systems, 2022

2021

Insights Into the Dynamics of Coupled VO<sub>2</sub> Oscillators for ONNs.

[BibT_eX]

[DOI]

Aida Todri-Sanial

Elisabetta Corti

Siegfried F. Karg

IEEE Trans. Circuits Syst. II Express Briefs, 2021

2020

An Approach to the Device-Circuit Co-Design of HyperFET Circuits.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Symposium on Circuits and Systems, 2020

Oscillatory Hebbian Rule (OHR): An adaption of the Hebbian rule to Oscillatory Neural Networks.

[BibT_eX]

[DOI]

Jafar Shamsi

Teresa Serrano-Gotarredona

Proceedings of the XXXV Conference on Design of Circuits and Integrated Systems, 2020

2019

Power and Speed Evaluation of Hyper-FET Circuits.

[BibT_eX]

[DOI]

IEEE Access, 2019

2018

Impact of the RT-level architecture on the power performance of tunnel transistor circuits.

[BibT_eX]

[DOI]

Int. J. Circuit Theory Appl., 2018

Inverting Versus Non-Inverting Dynamic Logic for Two-Phase Latch-free Nanopipelines.

[BibT_eX]

[DOI]

Hector J. Quintero

Proceedings of the 15th International Conference on Synthesis, 2018

2017

Exploring logic architectures suitable for TFETs devices.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Symposium on Circuits and Systems, 2017

2016

Impact of pipeline in the power performance of tunnel transistor circuits.

[BibT_eX]

[DOI]

Proceedings of the 26th International Workshop on Power and Timing Modeling, 2016

2014

Experimental Validation of a Two-Phase Clock Scheme for Fine-Grained Pipelined Circuits Based on Monostable to Bistable Logic Elements.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2014

DOE based high-performance gate-level pipelines.

[BibT_eX]

[DOI]

Hector J. Quintero

Proceedings of the 24th International Workshop on Power and Timing Modeling, 2014

2013

Novel pipeline architectures based on Negative Differential Resistance devices.

[BibT_eX]

[DOI]

Microelectron. J., 2013

Novel Dynamic Gate Topology for Superpipelines in DSM Technologies.

[BibT_eX]

[DOI]

Proceedings of the 2013 Euromicro Conference on Digital System Design, 2013

2012

Two-Phase MOBILE Interconnection Schemes for Ultra-Grain Pipeline Applications.

[BibT_eX]

[DOI]

Proceedings of the Integrated Circuit and System Design. Power and Timing Modeling, 2012

Compact and Power Efficient MOS-NDR Muller C-Elements.

[BibT_eX]

[DOI]

Proceedings of the Technological Innovation for Value Creation, 2012

Bifurcation diagrams in MOS-NDR frequency divider circuits.

[BibT_eX]

[DOI]

Proceedings of the 19th IEEE International Conference on Electronics, Circuits and Systems, 2012

2011

Efficient realization of RTD-CMOS logic gates.

[BibT_eX]

[DOI]

Proceedings of the 21st ACM Great Lakes Symposium on VLSI 2010, 2011

2010

An improved RNS generator 2<sup>n</sup> +/- k based on threshold logic.

[BibT_eX]

[DOI]

Proceedings of the 18th IEEE/IFIP VLSI-SoC 2010, 2010

Single phase MOS-NDR mobile networks.

[BibT_eX]

[DOI]

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2010), May 30, 2010

Evaluation of RTD-CMOS Logic Gates.

[BibT_eX]

[DOI]

Proceedings of the 13th Euromicro Conference on Digital System Design, 2010

2009

Operation Limits for RTD-Based MOBILE Circuits.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. I Regul. Pap., 2009

Fast and Area Efficient Multi-input Muller C-Element based on MOS-NDR.

[BibT_eX]

[DOI]

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2009), 2009

2008

Using multi-threshold threshold gates in RTD-based logic design: A case study.

[BibT_eX]

[DOI]

Microelectron. J., 2008

A novel contribution to the RTD-based threshold logic family.

[BibT_eX]

[DOI]

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2008), 2008

Limits to a correct operation in RTD-based ternary inverters.

[BibT_eX]

[DOI]

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2008), 2008

Analysis of the critical rise time in MOBILE-based circuits.

[BibT_eX]

[DOI]

Proceedings of the 15th IEEE International Conference on Electronics, Circuits and Systems, 2008

2007

A quasi-differential quantizer based on SMOBILE.

[BibT_eX]

[DOI]

Proceedings of the 20th Annual Symposium on Integrated Circuits and Systems Design, 2007

Limits to a Correct Evaluation in RTD-Based Quaternary Inverters.

[BibT_eX]

[DOI]

Proceedings of the 37th International Symposium on Multiple-Valued Logic, 2007

Non Return Mobile Logic Family.

[BibT_eX]

[DOI]

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2007), 2007

Operation limits in RTD-based ternary quantizers.

[BibT_eX]

[DOI]

Proceedings of the 17th ACM Great Lakes Symposium on VLSI 2007, 2007

Correct operation in SMOBILE-based quasi-differential quantizers.

[BibT_eX]

[DOI]

Proceedings of the 18th European Conference on Circuit Theory and Design, 2007

2006

Self-latching operation of MOBILE circuits using series-connection of RTDs and transistors.

[BibT_eX]

[DOI]

Héctor Pettenghi Roldán

IEEE Trans. Circuits Syst. II Express Briefs, 2006

Self-latching operation limits for MOBILE circuits.

[BibT_eX]

[DOI]

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006

Limits to a Correct Evaluation in RTD-based Ternary Inverters.

[BibT_eX]

[DOI]

Proceedings of the 13th IEEE International Conference on Electronics, 2006

Monostable-Bistable Transition Logic Elements: Threshold Logic vs. Boolean Logic Comparison.

[BibT_eX]

[DOI]

Proceedings of the 13th IEEE International Conference on Electronics, 2006

Design Guides for a Correct DC Operation in RTD-based Threshold Gates.

[BibT_eX]

[DOI]

Proceedings of the Ninth Euromicro Conference on Digital System Design: Architectures, Methods and Tools (DSD 2006), 30 August, 2006

2005

Analysis of frequency divider RTD circuits.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. I Regul. Pap., 2005

Robust frequency divider based on resonant tunneling devices.

[BibT_eX]

[DOI]

José L. Huertas

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005

Logic Models Supporting the Design of MOBILE-based RTD Circuits.

[BibT_eX]

[DOI]

Proceedings of the 16th IEEE International Conference on Application-Specific Systems, 2005

2004

A Practical Parallel Architecture for Stacks Filters.

[BibT_eX]

[DOI]

Hamid El Alami

Antonio Jiménez-Calderón

J. VLSI Signal Process., 2004

Pass-transistor based implementations of threshold logic gates for WOS filtering.

[BibT_eX]

[DOI]

Raúl Jiménez-Naharro

Microelectron. J., 2004

Programmable logic gate based on resonant tunnelling devices.

[BibT_eX]

Proceedings of the 2004 International Symposium on Circuits and Systems, 2004

A Threshold Logic Synthesis Tool for RTD Circuits.

[BibT_eX]

[DOI]

Proceedings of the 2004 Euromicro Symposium on Digital Systems Design (DSD 2004), Architectures, Methods and Tools, 31 August, 2004

2003

VLSI implementations of threshold logic-a comprehensive survey.

[BibT_eX]

[DOI]

Valeriu Beiu

IEEE Trans. Neural Networks, 2003

Review of Differential Threshold Gate Implementations.

[BibT_eX]

Valeriu Beiu

Proceedings of the IASTED International Conference on Neural Networks and Computational Intelligence, 2003

Review of Capacitive Threshold Gate Implementations.

[BibT_eX]

[DOI]

Valeriu Beiu

Proceedings of the Artificial Neural Networks and Neural Information Processing, 2003

2002

COPAS: A New Algorithm for the Partial Input Encoding Problem.

[BibT_eX]

[DOI]

VLSI Design, 2002

High-speed low-power logic gates using floating gates.

[BibT_eX]

[DOI]

Adoración Rueda

Proceedings of the 2002 International Symposium on Circuits and Systems, 2002

Simplified Reed-Muller expressions for residue threshold functions.

[BibT_eX]

[DOI]

José L. Huertas

Proceedings of the 2002 International Symposium on Circuits and Systems, 2002

Simple parallel weighted order statistic filter implementations.

[BibT_eX]

[DOI]

Proceedings of the 2002 International Symposium on Circuits and Systems, 2002

Threshold-logic-based design of compressors.

[BibT_eX]

[DOI]

Adoración Rueda

Proceedings of the 2002 9th IEEE International Conference on Electronics, 2002

An Encoding Technique for Low Power CMOS Implementations of Controllers.

[BibT_eX]

[DOI]

Proceedings of the 2002 Design, 2002

2001

Efficient Realization of a Threshold Voter for Self-Purging Redundancy.

[BibT_eX]

[DOI]

José Luis Huertas

J. Electron. Test., 2001

Reed-Muller descriptions of symmetric functions.

[BibT_eX]

[DOI]

Proceedings of the 2001 International Symposium on Circuits and Systems, 2001

Low-power logic styles for full-adder circuits.

[BibT_eX]

[DOI]

Raúl Jiménez

Proceedings of the 2001 8th IEEE International Conference on Electronics, 2001

Practical low-cost CPL implementations threshold logic functions.

[BibT_eX]

[DOI]

Raúl Jiménez

Proceedings of the 11th ACM Great Lakes Symposium on VLSI 2001, 2001

Two-Criterial Constraint-Driven FSM State Encoding for Low Power.

[BibT_eX]

[DOI]

Proceedings of the Euromicro Symposium on Digital Systems Design 2001 (Euro-DSD 2001), 2001

2000

νMOS-based Sorter for Arithmetic Applications.

[BibT_eX]

[DOI]

VLSI Design, 2000

Efficient νMOS Realization of Threshold Voters for Self-Purging Redundancy.

[BibT_eX]

[DOI]

Adoración Rueda

Proceedings of the 13th Annual Symposium on Integrated Circuits and Systems Design, 2000

1999

vMOS-based sorters for multiplier implementations.

[BibT_eX]

[DOI]

Proceedings of the 1999 International Symposium on Circuits and Systems, ISCAS 1999, Orlando, Florida, USA, May 30, 1999

An Algorithm for Face-Constrained Encoding of Symbols Using Minimum Code Length.

[BibT_eX]

[DOI]

Proceedings of the 1999 Design, 1999

1998

A Dynamic Model for the State Assignment Problem.

[BibT_eX]

[DOI]

Proceedings of the 1998 Design, 1998

1995

Constrained state assignment of easily testable FSMs.

[BibT_eX]

[DOI]

José Luis Huertas

J. Electron. Test., 1995

Optimum PLA folding through boolean satisfiability.

[BibT_eX]

[DOI]

Proceedings of the 1995 Conference on Asia Pacific Design Automation, Makuhari, Massa, Chiba, Japan, August 29, 1995

1993

Easily Testable PLA-based FSMS.

[BibT_eX]

José L. Huertas

Proceedings of the 1993 IEEE International Symposium on Circuits and Systems, 1993

1990

A new method for the state reduction of incompletely specified finite sequential machines.

[BibT_eX]

[DOI]