Kazutoshi Wakabayashi

According to our database1, Kazutoshi Wakabayashi authored at least 51 papers between 1985 and 2024.

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Bibliography

2024
ISP Parameter Optimization and FPGA Implementation for Object Detection in Low-Light Conditions.
Proceedings of the IEEE Symposium in Low-Power and High-Speed Chips, 2024

2021
A programming environment for multi-FPGA systems based on CyberWorkBench: an integrated design tool.
Proceedings of the HEART '21: 11th International Symposium on Highly Efficient Accelerators and Reconfigurable Technologies, 2021

2020
33.3 Via-Switch FPGA: 65nm CMOS Implementation and Architecture Extension for Al Applications.
Proceedings of the 2020 IEEE International Solid- State Circuits Conference, 2020

2019
Convolution Neural Network Development Support System using Approximation Methods to Evaluate Inference Accuracy and Memory Usage in an Embedded System.
Proceedings of the 2019 IEEE SmartWorld, 2019

2018
Via-Switch FPGA: Highly Dense Mixed-Grained Reconfigurable Architecture With Overlay Via-Switch Crossbars.
IEEE Trans. Very Large Scale Integr. Syst., 2018

Sensor Signal Processing Using High-Level Synthesis With a Layered Architecture.
IEEE Embed. Syst. Lett., 2018

2016
Range Limiter Using Connection Bounding Box for SA-Based Placement of Mixed-Grained Reconfigurable Architecture.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2016

A highly-dense mixed grained reconfigurable architecture with overlay crossbar interconnect using via-switch.
Proceedings of the 26th International Conference on Field Programmable Logic and Applications, 2016

2015
Reliability-configurable mixed-grained reconfigurable array compatible with high-level synthesis.
Proceedings of the 20th Asia and South Pacific Design Automation Conference, 2015

2014
Reliability-Configurable Mixed-Grained Reconfigurable Array Supporting C-Based Design and Its Irradiation Testing.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2014

Mapping complex algorithm into FPGA with High Level Synthesis reconfigurable chips with High Level Synthesis compared with CPU, GPGPU.
Proceedings of the 19th Asia and South Pacific Design Automation Conference, 2014

2013
Mixed-grained reconfigurable architecture supporting flexible reliability and C-based design.
Proceedings of the 2012 International Conference on Reconfigurable Computing and FPGAs, 2013

Reconfigurable chip advantage compared with GPGPU from the compiler perspective.
Proceedings of the 2013 International Conference on Field-Programmable Technology, 2013

2012
Divide and conquer high-level synthesis design space exploration.
ACM Trans. Design Autom. Electr. Syst., 2012

Machine learning predictive modelling high-level synthesis design space exploration.
IET Comput. Digit. Tech., 2012

2011
Precision tunable RTL macro-modelling cycle-accurate power estimation.
IET Comput. Digit. Tech., 2011

Iterative Synthesis Methods Estimating Programmable-Wire Congestion in a Dynamically Reconfigurable Processor.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2011

2010
Design Space Exploration Acceleration Through Operation Clustering.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2010

High-level Synthesis Challenges for Mapping a Complete Program on a Dynamically Reconfigurable Processor.
IPSJ Trans. Syst. LSI Des. Methodol., 2010

Foreword.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2010

Fixed Point Data Type Modeling for High Level Synthesis.
IEICE Trans. Electron., 2010

CODES+ISSS 2009 guest editors' introduction.
Des. Autom. Embed. Syst., 2010

Exploiting power budgeting in thermal-aware dynamic placement for reconfigurable systems.
Proceedings of the 2010 International Symposium on Low Power Electronics and Design, 2010

Wire congestion aware synthesis for a dynamically reconfigurable processor.
Proceedings of the International Conference on Field-Programmable Technology, 2010

Real-time multimedia with C compiler for Hardware.
Proceedings of the 8th IEEE Workshop on Embedded Systems for Real-Time Multimedia, 2010

Design of complex image processing systems in ESL.
Proceedings of the 15th Asia South Pacific Design Automation Conference, 2010

2008
The State of ESL Design [Roundtable].
IEEE Des. Test Comput., 2008

2007
Max-Flow Scheduling in High-Level Synthesis.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2007

Synthesizing "Verification Aware" Models: Why and How?
Proceedings of the 20th International Conference on VLSI Design (VLSI Design 2007), 2007

2006
Unified Representation for Speculative Scheduling: Generalized Condition Vector.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2006

High-level synthesis challenges and solutions for a dynamically reconfigurable processor.
Proceedings of the 2006 International Conference on Computer-Aided Design, 2006

2005
System LSI design with C-based behavioral synthesis and verification.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005

Are we ready for system-level synthesis?
Proceedings of the 2005 Conference on Asia South Pacific Design Automation, 2005

2004
Stream applications on the dynamically reconfigurable processor.
Proceedings of the 2004 IEEE International Conference on Field-Programmable Technology, 2004

Implementing and Evaluating Stream Applications on the Dynamically Reconfigurable Processor.
Proceedings of the 12th IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM 2004), 2004

C-based behavioral synthesis and verification analysis on industrial design examples.
Proceedings of the 2004 Conference on Asia South Pacific Design Automation: Electronic Design and Solution Fair 2004, 2004

2003
Study and Analysis of System LSI Design Methodologies Using C-Based Behavioral Synthesis.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2003

2002
Property-Specific Testbench Generation for Guided Simulation.
Proceedings of the 7th Asia and South Pacific Design Automation Conference (ASP-DAC 2002), 2002

2001
Property-specific witness graph generation for guided simulation.
Proceedings of the Conference on Design, Automation and Test in Europe, 2001

2000
C-based SoC design flow and EDA tools: an ASIC and system vendorperspective.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2000

Spatial-temporal mapping of real applications on a Dynamically Reconfigurable Logic Engine (DRLE) LSI.
Proceedings of the IEEE 2000 Custom Integrated Circuits Conference, 2000

1999
Controller-based power management for control-flow intensive designs.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1999

C-based Synthesis Experiences with a Behavior Synthesizer, "Cyber".
Proceedings of the 1999 Design, 1999

1997
Power Management Techniques for Control-Flow Intensive Designs.
Proceedings of the 34st Conference on Design Automation, 1997

1996
Controller re-specification to minimize switching activity in controller/data path circuits.
Proceedings of the 1996 International Symposium on Low Power Electronics and Design, 1996

1995
Design-for-debugging of application specific designs.
Proceedings of the 1995 IEEE/ACM International Conference on Computer-Aided Design, 1995

Efficient throughput optimization of feedback linear computations using generalized Horner's scheme.
Proceedings of the 1995 International Conference on Acoustics, 1995

Multi-Level Logic Minimization Based on Multi-Signal Implications.
Proceedings of the 32st Conference on Design Automation, 1995

1992
Global Scheduling Independent of Control Dependencies Based on Condition Vectors.
Proceedings of the 29th Design Automation Conference, 1992

1989
A resource sharing and control synthesis method for conditional branches.
Proceedings of the 1989 IEEE International Conference on Computer-Aided Design, 1989

1985
Knowledge-based placement technique for printed wiring boards.
Proceedings of the 22nd ACM/IEEE conference on Design automation, 1985


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