Jean-Jacques Hajjar

According to our database1, Jean-Jacques Hajjar authored at least 12 papers between 2012 and 2024.

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Bibliography

2024
Reduced RC Time Constant High Voltage Tolerant Supply Clamp for ESD Protection in 16nm FinFET Technology.
Proceedings of the IEEE International Reliability Physics Symposium, 2024

2023
Optimization of SCR for High-Speed Digital and RF Applications in 45-nm SOI CMOS Technology.
Proceedings of the IEEE International Reliability Physics Symposium, 2023

2022
A High Voltage Tolerant Supply Clamp for ESD Protection in a 45-nm SOI Technology.
Proceedings of the IEEE International Reliability Physics Symposium, 2022

2019
Characterization and Modeling of the Transient Safe Operating Area in LDMOS Transistors.
Proceedings of the IEEE International Reliability Physics Symposium, 2019

2017
ESD protection structure with reduced capacitance and overshoot voltage for high speed interface applications.
Microelectron. Reliab., 2017

2015
Design and characterization of ESD solutions with EMC robustness for automotive applications.
Microelectron. Reliab., 2015

Compact failure modeling for devices subject to electrostatic discharge stresses - A review pertinent to CMOS reliability simulation.
Microelectron. Reliab., 2015

ESD protection clamp with active feedback and mis-trigger immunity in 28nm CMOS process.
Proceedings of the IEEE International Reliability Physics Symposium, 2015

2014
Design optimization of SiGe BiCMOS Silicon Controlled Rectifier for Charged Device Model (CDM) protection applications.
Microelectron. Reliab., 2014

2013
vfTLP-V<sub>TH</sub>: A new method for quantifying the effectiveness of ESD protection for the CDM classification test.
Microelectron. Reliab., 2013

Investigation on effectiveness of series gate resistor in CDM ESD protection designs.
Proceedings of the IEEE 10th International Conference on ASIC, 2013

2012
Modeling of high voltage devices for ESD event simulation in SPICE.
Microelectron. J., 2012


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