Jan Hoogerbrugge

According to our database1, Jan Hoogerbrugge authored at least 23 papers between 1991 and 2021.

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Bibliography

2021
CrypTag: Thwarting Physical and Logical Memory Vulnerabilities using Cryptographically Colored Memory.
Proceedings of the ASIA CCS '21: ACM Asia Conference on Computer and Communications Security, 2021

2013
Variation tolerance and error resilience in a low power wireless receiver.
Proceedings of the 2013 IEEE 31st International Conference on Computer Design, 2013

Design of a multi GBPS Single Carrier digital baseband for 60GHz applications and its FPGA implementation.
Proceedings of the 23rd International Conference on Field programmable Logic and Applications, 2013

2012
Balancing Programmability and Silicon Efficiency of Heterogeneous Multicore Architectures.
ACM Trans. Embed. Comput. Syst., 2012

2011
A Multithreaded Multicore System for Embedded Media Processing.
Trans. High Perform. Embed. Archit. Compil., 2011

A Highly Scalable Parallel Implementation of H.264.
Trans. High Perform. Embed. Archit. Compil., 2011

2009
Parallel H.264 Decoding on an Embedded Multicore Processor.
Proceedings of the High Performance Embedded Architectures and Compilers, 2009

2001
Exploring design space of parallel realizations: MPEG-2 decoder case study.
Proceedings of the Ninth International Symposium on Hardware/Software Codesign, 2001

2000
Compiling Applications for ConCISe: An Example of Automatic HW/SW Partitioning and Synthesis.
Proceedings of the Field-Programmable Logic and Applications, 2000

Cost-Efficient Branch Target Buffers.
Proceedings of the Euro-Par 2000, Parallel Processing, 6th International Euro-Par Conference, Munich, Germany, August 29, 2000

Pipelined Java Virtual Machine Interpreters.
Proceedings of the Compiler Construction, 9th International Conference, 2000

Dynamic Branch Prediction for a VLIW Processor.
Proceedings of the 2000 International Conference on Parallel Architectures and Compilation Techniques (PACT'00), 2000

1999
A Code Compression System Based on Pipelined Interpreters.
Softw. Pract. Exp., 1999

Instruction Scheduling for TriMedia.
J. Instr. Level Parallelism, 1999

ConCISe: A Compiler-Driven CPLD-Based Instruction Set Accelerator.
Proceedings of the 7th IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM '99), 1999

OCEANS - Optimising Compilers for Embedded Applications.
Proceedings of the Euro-Par '99 Parallel Processing, 5th International Euro-Par Conference, Toulouse, France, August 31, 1999

1998

1997

1994
Register file port requirements of transport triggered architectures.
Proceedings of the 27th Annual International Symposium on Microarchitecture, San Jose, California, USA, November 30, 1994

Code generation for transport triggered architectures.
Proceedings of the Code Generation for Embedded Processors [Dagstuhl Workshop, Dagstuhl, Germany, August 31, 1994

Transport-Triggering versus Operation-Triggering.
Proceedings of the Compiler Construction, 5th International Conference, 1994

1992
Comparing Software Pipelining for an Operation-Triggered and a Tarnsport-Triggered Architecture.
Proceedings of the Compiler Construction, 1992

1991
Software Pipelining for Transport-Triggered Architectures.
Proceedings of the 24th Annual IEEE/ACM International Symposium on Microarchitecture, 1991


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