Henri-Pierre Charles
Orcid: 0000-0002-0119-0446
According to our database1,
Henri-Pierre Charles
authored at least 45 papers
between 1989 and 2023.
Collaborative distances:
Collaborative distances:
Timeline
Legend:
Book In proceedings Article PhD thesis Dataset OtherLinks
Online presence:
-
on orcid.org
On csauthors.net:
Bibliography
2023
Dedicated Instruction Set for Pattern-Based Data Transfers: An Experimental Validation on Systems Containing In-Memory Computing Units.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., November, 2023
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2023
2022
Towards a Truly Integrated Vector Processing Unit for Memory-bound Applications Based on a Cost-competitive Computational SRAM Design Solution.
ACM J. Emerg. Technol. Comput. Syst., 2022
2021
Instruction Set Design Methodology for In-Memory Computing through QEMU-based System Emulator.
Proceedings of the IEEE International Workshop on Rapid System Prototyping, 2021
Data Management Model to Program Irregular Compute Kernels on FPGA: Application to Heterogeneous Distributed System.
Proceedings of the Euro-Par 2021: Parallel Processing Workshops, 2021
2020
Data-layout optimization based on memory-access-pattern analysis for source-code performance improvement.
Proceedings of the SCOPES '20: 23rd International Workshop on Software and Compilers for Embedded Systems, 2020
A combined fast/cycle accurate simulation tool for reconfigurable accelerator evaluation: application to distributed data management.
Proceedings of the International Workshop on Rapid System Prototyping, 2020
Reconfigurable tiles of computing-in-memory SRAM architecture for scalable vectorization.
Proceedings of the ISLPED '20: ACM/IEEE International Symposium on Low Power Electronics and Design, 2020
Proceedings of the 22nd International Conference on Advanced Communication Technology, 2020
Computational SRAM Design Automation using Pushed-Rule Bitcells for Energy-Efficient Vector Processing.
Proceedings of the 2020 Design, Automation & Test in Europe Conference & Exhibition, 2020
2019
ACM Trans. Archit. Code Optim., 2019
Proceedings of the 27th IFIP/IEEE International Conference on Very Large Scale Integration, 2019
Proceedings of the 30th International Workshop on Rapid System Prototyping, 2019
2018
Smart instruction codes for in-memory computing architectures compatible with standard SRAM interfaces.
Proceedings of the 2018 Design, Automation & Test in Europe Conference & Exhibition, 2018
Proceedings of the Cyber-Physical Systems Security., 2018
2017
Proceedings of the International Symposium on Rapid System Prototyping, 2017
2016
A New Compilation Flow for Software-Defined Radio Applications on Heterogeneous MPSoCs.
ACM Trans. Archit. Code Optim., 2016
Pushing the Limits of Online Auto-Tuning: Machine Code Optimization in Short-Running Kernels.
Proceedings of the 10th IEEE International Symposium on Embedded Multicore/Many-core Systems-on-Chip, 2016
DRC<sup>2</sup>: Dynamically Reconfigurable Computing Circuit based on memory architecture.
Proceedings of the IEEE International Conference on Rebooting Computing, 2016
Proceedings of the 17th International Conference on Distributed Computing and Networking, 2016
2015
Proceedings of the 18th International Workshop on Software and Compilers for Embedded Systems, 2015
FPU Speedup Estimation for Task Placement Optimization on Asymmetric Multicore Designs.
Proceedings of the IEEE 9th International Symposium on Embedded Multicore/Many-core Systems-on-Chip, 2015
Proceedings of the 2015 Workshop on Rapid Simulation and Performance Evaluation: Methods and Tools, 2015
2014
Hardware Acceleration of Red-Black Tree Management and Application to Just-In-Time Compilation.
J. Signal Process. Syst., 2014
Performance comparison between Java and JNI for optimal implementation of computational micro-kernels.
CoRR, 2014
Micro-architectural simulation of in-order and out-of-order ARM microprocessors with gem5.
Proceedings of the XIVth International Conference on Embedded Computer Systems: Architectures, 2014
Proceedings of the Compiler Construction - 23rd International Conference, 2014
A compilation flow for parametric dataflow: Programming model, scheduling, and application to heterogeneous MPSoC.
Proceedings of the 2014 International Conference on Compilers, 2014
2013
Proceedings of the Parallel Computing: Accelerating Computational Science and Engineering (CSE), 2013
Hardware acceleration for Just-In-Time compilation on heterogeneous embedded systems.
Proceedings of the 24th International Conference on Application-Specific Systems, 2013
2009
Concurr. Comput. Pract. Exp., 2009
2008
Proceedings of the 2008 ACM Symposium on Applied Computing (SAC), 2008
2007
Proceedings of the Languages and Compilers for Parallel Computing, 2007
Proceedings of the 16th International Conference on Parallel Architectures and Compilation Techniques (PACT 2007), 2007
2006
Proceedings of the Languages and Compilers for Parallel Computing, 2006
2005
Proceedings of the 9th International Workshop on Software and Compilers for Embedded Systems, Dallas, Texas, USA, September 29, 2005
2004
Data cache management on EPIC architecture: optimizing memory access for image processing.
SIGARCH Comput. Archit. News, 2004
Proceedings of the 7th Workshop on languages, 2004
1999
Proceedings of the Euro-Par '99 Parallel Processing, 5th International Euro-Par Conference, Toulouse, France, August 31, 1999
1998
Proceedings of the Euro-Par '98 Parallel Processing, 1998
1997
Proceedings of the Euro-Par '97 Parallel Processing, 1997
1993
Parallel Process. Lett., 1993
1992
1991
Loop unrolling for processors with instruction cache.
Proceedings of the Algorithms and Parallel VLSI Architectures II, 1991
1989
Microprocessing and Microprogramming, 1989