Hiroshi Makino
Orcid: 0000-0001-6444-133X
According to our database1,
Hiroshi Makino
authored at least 46 papers
between 1980 and 2016.
Collaborative distances:
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Bibliography
2016
A Field Programmable Sequencer and Memory with Middle Grained Programmability Optimized for MCU Peripherals.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2016
Proceedings of the IEEE 5th Global Conference on Consumer Electronics, 2016
Proceedings of the IEEE 5th Global Conference on Consumer Electronics, 2016
2015
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2015
2014
Increase in Read Noise Margin of Single-Bit-Line SRAM Using Adiabatic Change of Word Line Voltage.
IEEE Trans. Very Large Scale Integr. Syst., 2014
Energy Efficient Stepwise Charging of a Capacitor Using a DC-DC Converter With Consecutive Changes of its Duty Ratio.
IEEE Trans. Circuits Syst. I Regul. Pap., 2014
Analysis of voltage, Current and Energy dissipation of Stepwise Adiabatic Charging of a capacitor using a nonresonant inductor Current.
J. Circuits Syst. Comput., 2014
A new stepwise adiabatic charging circuit with a smaller capacitance in a regenerator than a load capacitance.
Proceedings of the IEEE 57th International Midwest Symposium on Circuits and Systems, 2014
The LSI implementation of a memory based field programmable device for MCU peripherals.
Proceedings of the 17th International Symposium on Design and Diagnostics of Electronic Circuits & Systems, 2014
2013
Analysis of Pull-in Range Limit by Charge Pump Mismatch in a Linear Phase-Locked Loop.
IEEE Trans. Circuits Syst. I Regul. Pap., 2013
2012
General Stability of Stepwise Waveform of an Adiabatic Charge Recycling Circuit With Any Circuit Topology.
IEEE Trans. Circuits Syst. I Regul. Pap., 2012
Utilising the normal distribution of the write noise margin to easily predict the SRAM write yield.
IET Circuits Devices Syst., 2012
Energy dissipation reduction during adiabatic charging and discharging with controlled inductor current.
Proceedings of the 55th IEEE International Midwest Symposium on Circuits and Systems, 2012
2011
Reexamination of SRAM Cell Write Margin Definitions in View of Predicting the Distribution.
IEEE Trans. Circuits Syst. II Express Briefs, 2011
2010
Stable adiabatic circuit using advanced series capacitors and time variation of energy dissipation.
IEICE Electron. Express, 2010
Adiabatic SRAM with a shared access port using a controlled ground line and step-voltage circuit.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2010), May 30, 2010
2009
Synchronous Ultra-High-Density 2RW Dual-Port 8T-SRAM With Circumvention of Simultaneous Common-Row-Access.
IEEE J. Solid State Circuits, 2009
2008
A 65 nm Embedded SRAM With Wafer Level Burn-In Mode, Leak-Bit Redundancy and Cu E-Trim Fuse for Known Good Die.
IEEE J. Solid State Circuits, 2008
A 45-nm Bulk CMOS Embedded SRAM With Improved Immunity Against Process and Temperature Variations.
IEEE J. Solid State Circuits, 2008
A 45 nm 2-port 8T-SRAM Using Hierarchical Replica Bitline Technique With Immunity From Simultaneous R/W Access Issues.
IEEE J. Solid State Circuits, 2008
A Large-Scale, Flip-Flop RAM Imitating a Logic LSI for Fast Development of Process Technology.
IEICE Trans. Electron., 2008
Post-silicon programmed body-biasing platform suppressing device variability in 45 nm CMOS technology.
Proceedings of the 2008 International Symposium on Low Power Electronics and Design, 2008
On-chip leakage monitor circuit to scan optimal reverse bias voltage for adaptive body-bias circuit under gate induced drain leakage effect.
Proceedings of the ESSCIRC 2008, 2008
2007
A 65-nm SoC Embedded 6T-SRAM Designed for Manufacturability With Read and Write Operation Stabilizing Circuits.
IEEE J. Solid State Circuits, 2007
Research and Commercialization of SCARA Robot -The Case of Industry-University Joint Research and Development-.
Int. J. Autom. Technol., 2007
A 45nm Low-Standby-Power Embedded SRAM with Improved Immunity Against Process and Temperature Variations.
Proceedings of the 2007 IEEE International Solid-State Circuits Conference, 2007
A 65nm Embedded SRAM with Wafer-Level Burn-In Mode, Leak-Bit Redundancy and E-Trim Fuse for Known Good Die.
Proceedings of the 2007 IEEE International Solid-State Circuits Conference, 2007
Fine-Grained In-Circuit Continuous-Time Probing Technique of Dynamic Supply Variations in SoCs.
Proceedings of the 2007 IEEE International Solid-State Circuits Conference, 2007
2005
A 32×24-bit multiplier-accumulator with advanced rectangular styled Wallace-tree structure.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005
Worst-case analysis to obtain stable read/write DC margin of high density 6T-SRAM-array with local Vth variability.
Proceedings of the 2005 International Conference on Computer-Aided Design, 2005
2004
A 90-nm low-power 32-kB embedded SRAM with gate leakage suppression circuit for mobile applications.
IEEE J. Solid State Circuits, 2004
2001
IEEE J. Solid State Circuits, 2001
1998
Proceedings of the 1998 International Symposium on Low Power Electronics and Design, 1998
1997
Comments on "Leading-zero anticipatory logic for high-speed floating point addition" [with reply].
IEEE J. Solid State Circuits, 1997
A Floating Point Divider using Redundant Binary Circuits and an Asynchronous Clock Scheme.
Proceedings of the Proceedings 1997 International Conference on Computer Design: VLSI in Computers & Processors, 1997
1996
IEEE J. Solid State Circuits, 1996
IEEE J. Solid State Circuits, 1996
IEEE J. Solid State Circuits, 1996
1995
1993
Proceedings of the Proceedings 1993 International Conference on Computer Design: VLSI in Computers & Processors, 1993
1989
1985
1980
An Automatic Translation System Of Non-Segmented Kana Sentences Into Kanji-Kana Sentences.
Proceedings of the 8th International Conference on Computational Linguistics, 1980