Dustin Richmond

Orcid: 0000-0002-4587-8947

According to our database1, Dustin Richmond authored at least 23 papers between 2013 and 2024.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

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Bibliography

2024
Pentimento: Data Remanence in Cloud FPGAs.
Proceedings of the 29th ACM International Conference on Architectural Support for Programming Languages and Operating Systems, 2024

2023
Turn on, Tune in, Listen up: Maximizing Side-Channel Recovery in Time-to-Digital Converters.
Proceedings of the 2023 ACM/SIGDA International Symposium on Field Programmable Gate Arrays, 2023

Beyond Static Parallel Loops: Supporting Dynamic Task Parallelism on Manycore Architectures with Software-Managed Scratchpad Memories.
Proceedings of the 28th ACM International Conference on Architectural Support for Programming Languages and Operating Systems, 2023

2022
A Tensor Processing Framework for CPU-Manycore Heterogeneous Systems.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022

2021
Taming the Zoo: The Unified GraphIt Compiler Framework for Novel Architectures.
Proceedings of the 48th ACM/IEEE Annual International Symposium on Computer Architecture, 2021

Classifying Computations on Multi-Tenant FPGAs.
Proceedings of the FPGA '21: The 2021 ACM/SIGDA International Symposium on Field Programmable Gate Arrays, Virtual Event, USA, February 28, 2021

A Tunable Dual-Edge Time-to-Digital Converter.
Proceedings of the 29th IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, 2021

Classifying Computations on Multi-Tenant FPGAs.
Proceedings of the 58th ACM/IEEE Design Automation Conference, 2021

2020
ASIC clouds: specializing the datacenter for planet-scale applications.
Commun. ACM, 2020

NoC Symbiosis : (Special Session Paper).
Proceedings of the 14th IEEE/ACM International Symposium on Networks-on-Chip, 2020

Ruche Networks: Wire-Maximal, No-Fuss NoCs : Special Session Paper.
Proceedings of the 14th IEEE/ACM International Symposium on Networks-on-Chip, 2020

2019
A 1.4 GHz 695 Giga Risc-V Inst/s 496-Core Manycore Processor With Mesh On-Chip Network and an All-Digital Synthesized PLL in 16nm CMOS.
Proceedings of the 2019 Symposium on VLSI Circuits, Kyoto, Japan, June 9-14, 2019, 2019

2018
Hardware Development for Non-Hardware Engineers.
PhD thesis, 2018

Synthesizable Higher-Order Functions for C++.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2018

Everyone's a Critic: A Tool for Exploring RISC-V Projects.
Proceedings of the 28th International Conference on Field Programmable Logic and Applications, 2018

PynqCopter - An Open-source FPGA Overlay for UAVs.
Proceedings of the IEEE International Conference on Big Data (IEEE BigData 2018), 2018

2017
A streaming clustering approach using a heterogeneous system for big data analysis.
Proceedings of the 2017 IEEE/ACM International Conference on Computer-Aided Design, 2017

2016
Resolve: Generation of High-Performance Sorting Architectures from High-Level Synthesis.
Proceedings of the 2016 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, 2016

Tinker: Generating Custom Memory Architectures for Altera's OpenCL Compiler.
Proceedings of the 24th IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, 2016

2015
RIFFA 2.1: A Reusable Integration Framework for FPGA Accelerators.
ACM Trans. Reconfigurable Technol. Syst., 2015

2014
Enabling FPGAs for the Masses.
CoRR, 2014

Real-time 3D reconstruction for FPGAs: A case study for evaluating the performance, area, and programmability trade-offs of the Altera OpenCL SDK.
Proceedings of the 2014 International Conference on Field-Programmable Technology, 2014

2013
A FPGA design for high speed feature extraction from a compressed measurement stream.
Proceedings of the 23rd International Conference on Field programmable Logic and Applications, 2013


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