Andres Meza

Orcid: 0000-0002-4283-0833

Affiliations:
  • University of California San Diego, Department of Computer Science and Engineering, La Jolla, CA, USA


According to our database1, Andres Meza authored at least 18 papers between 2021 and 2024.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

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Links

Online presence:

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Bibliography

2024
Tailor: Altering Skip Connections for Resource-Efficient Inference.
ACM Trans. Reconfigurable Technol. Syst., March, 2024


Pentimento: Data Remanence in Cloud FPGAs.
Proceedings of the 29th ACM International Conference on Architectural Support for Programming Languages and Operating Systems, 2024

2023
Isadora: automated information-flow property generation for hardware security verification.
J. Cryptogr. Eng., November, 2023

A Framework for Design, Verification, and Management of SoC Access Control Systems.
IEEE Trans. Computers, February, 2023

Security Verification of the OpenTitan Hardware Root of Trust.
IEEE Secur. Priv., 2023

Information Flow Coverage Metrics for Hardware Security Verification.
CoRR, 2023

Special Session: CAD for Hardware Security - Promising Directions for Automation of Security Assurance.
Proceedings of the 41st IEEE VLSI Test Symposium, 2023

ChimpACT: A Longitudinal Dataset for Understanding Chimpanzee Behaviors.
Proceedings of the Advances in Neural Information Processing Systems 36: Annual Conference on Neural Information Processing Systems 2023, 2023

Automated Generation, Verification, and Ranking of Secure SoC Access Control Policies.
Proceedings of Cyber-Physical Systems and Internet of Things Week 2023, 2023

2022
Toward Hardware Security Property Generation at Scale.
IEEE Secur. Priv., 2022

Open-source FPGA-ML codesign for the MLPerf Tiny Benchmark.
CoRR, 2022

Automating hardware security property generation: invited.
Proceedings of the DAC '22: 59th ACM/IEEE Design Automation Conference, San Francisco, California, USA, July 10, 2022

2021
Applications and Techniques for Fast Machine Learning in Science.
CoRR, 2021

AKER: A Design and Verification Framework for Safe andSecure SoC Access Control.
CoRR, 2021

A Methodology For Creating Information Flow Specifications of Hardware Designs.
CoRR, 2021

Aker: A Design and Verification Framework for Safe and Secure SoC Access Control.
Proceedings of the IEEE/ACM International Conference On Computer Aided Design, 2021

Isadora: Automated Information Flow Property Generation for Hardware Designs.
Proceedings of the ASHES@CCS 2021: Proceedings of the 5th Workshop on Attacks and Solutions in Hardware Security, 2021


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