Chaoyang Zheng

According to our database, Chaoyang Zheng authored at least 5 papers between 2015 and 2024.

Collaborative distances:

• Dijkstra number of three.
• Erdős number of three.

2024

Global exponential synchronization of complex networks with reaction diffusions and finite distributed delays coupling.

Yun Xing, Chaoyang Zheng, Yin Sheng, Zhigang Zeng

Neurocomputing, 2024

2023

A 400M-510MHz On-Chip Transformer-Based RF Power Amplifier with 22.5dBm Output Power and 48% PAE.

Chaoyang Zheng, Zhipeng Chen, Jianhua Lu, Yan Ma, Yumei Huang, Zhiliang Hong

Proceedings of the 15th IEEE International Conference on ASIC, 2023

2021

Multi-Scale Feedback Feature Refinement U-Net for Medical Image Segmentation.

Xiaofei Qin, Minmin Xu, Chaoyang Zheng, Changxiang He, Xuedian Zhang

Proceedings of the 2021 IEEE International Conference on Multimedia and Expo, 2021

2016

SPARC M7: A 20 nm 32-Core 64 MB L3 Cache Processor.

Georgios K. Konstadinidis, Hongping Penny Li, Francis Schumacher, Venkatram Krishnaswamy, Hoyeol Cho, Sudesna Dash, Robert P. Masleid, Chaoyang Zheng, Yuanjung David Lin, Paul Loewenstein, Heechoul Park, Vijay Srinivasan, Dawei Huang, Changku Hwang, Wenjay Hsu, Curtis McAllister, Jeffrey Brooks, Ha Pham, Sebastian Turullols, Yifan YangGong, Robert T. Golla, Alan P. Smith, Ali Vahidsafa

IEEE J. Solid State Circuits, 2016

2015

4.2 A 20nm 32-Core 64MB L3 cache SPARC M7 processor.

Penny Li, Jinuk Luke Shin, Georgios K. Konstadinidis, Francis Schumacher, Venkatram Krishnaswamy, Hoyeol Cho, Sudesna Dash, Robert P. Masleid, Chaoyang Zheng, Yuanjung David Lin, Paul Loewenstein, Heechoul Park, Vijay Srinivasan, Dawei Huang, Changku Hwang, Wenjay Hsu, Curtis McAllister

Proceedings of the 2015 IEEE International Solid-State Circuits Conference, 2015