Changku Hwang

According to our database1, Changku Hwang authored at least 7 papers between 1996 and 2016.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of two.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Dataset
Other 

Links

On csauthors.net:

Bibliography

2016
SPARC M7: A 20 nm 32-Core 64 MB L3 Cache Processor.
IEEE J. Solid State Circuits, 2016

2015

2014
A 3.6 GHz 16-Core SPARC SoC Processor in 28 nm.
IEEE J. Solid State Circuits, 2014

2013

2011
A 40 nm 16-Core 128-Thread SPARC SoC Processor.
IEEE J. Solid State Circuits, 2011

2010
A 40nm 16-core 128-thread CMT SPARC SoC processor.
Proceedings of the IEEE International Solid-State Circuits Conference, 2010

1996
On-Chip I<sub>DDQ</sub> testability schemes for detecting multiple faults in CMOS ICs.
IEEE J. Solid State Circuits, 1996


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