Ann Franchesca Laguna

Orcid: 0000-0001-8267-1040

According to our database1, Ann Franchesca Laguna authored at least 24 papers between 2014 and 2023.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

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On csauthors.net:

Bibliography

2023
A Reconfigurable FeFET Content Addressable Memory for Multi-State Hamming Distance.
IEEE Trans. Circuits Syst. I Regul. Pap., 2023

Invited Paper: Algorithm/Hardware Co-Design for Few-Shot Learning at the Edge.
Proceedings of the IEEE/ACM International Conference on Computer Aided Design, 2023

Development of a Computer Vision-Based Road Physical Feature Extraction.
Proceedings of the IEEE International Conference on Big Data, 2023

In-Memory Computing Accelerators for Emerging Learning Paradigms.
Proceedings of the 28th Asia and South Pacific Design Automation Conference, 2023

2022
FeFET Multi-Bit Content-Addressable Memories for In-Memory Nearest Neighbor Search.
IEEE Trans. Computers, 2022

Experimentally realized memristive memory augmented neural network.
CoRR, 2022

COSIME: FeFET Based Associative Memory for In-Memory Cosine Similarity Search.
Proceedings of the 41st IEEE/ACM International Conference on Computer-Aided Design, 2022

Associative Memory Based Experience Replay for Deep Reinforcement Learning.
Proceedings of the 41st IEEE/ACM International Conference on Computer-Aided Design, 2022

iMARS: an in-memory-computing architecture for recommendation systems.
Proceedings of the DAC '22: 59th ACM/IEEE Design Automation Conference, San Francisco, California, USA, July 10, 2022

2021
Deep Random Forest with Ferroelectric Analog Content Addressable Memory.
CoRR, 2021

ICCAD Tutorial Session Paper Ferroelectric FET Technology and Applications: From Devices to Systems.
Proceedings of the IEEE/ACM International Conference On Computer Aided Design, 2021

Exploiting FeFETs via Cross-Layer Design from In-memory Computing Circuits to Meta-Learning Applications.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2021

In-Memory Computing based Accelerator for Transformer Networks for Long Sequences.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2021

In-Memory Nearest Neighbor Search with FeFET Multi-Bit Content-Addressable Memories.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2021

Attention-in-Memory for Few-Shot Learning with Configurable Ferroelectric FET Arrays.
Proceedings of the ASPDAC '21: 26th Asia and South Pacific Design Automation Conference, 2021

Cross-layer Design for Computing-in-Memory: From Devices, Circuits, to Architectures and Applications.
Proceedings of the ASPDAC '21: 26th Asia and South Pacific Design Automation Conference, 2021

2020
The Impact of Ferroelectric FETs on Digital and Analog Circuits and Architectures.
IEEE Des. Test, 2020

Seed-and-Vote based In-Memory Accelerator for DNA Read Mapping.
Proceedings of the IEEE/ACM International Conference On Computer Aided Design, 2020

A Fast and Energy Efficient Computing-in-Memory Architecture for Few-Shot Learning Applications.
Proceedings of the 2020 Design, Automation & Test in Europe Conference & Exhibition, 2020

Emerging Neural Workloads and Their Impact on Hardware.
Proceedings of the 2020 Design, Automation & Test in Europe Conference & Exhibition, 2020

2019
Ferroelectric FET Based In-Memory Computing for Few-Shot Learning.
Proceedings of the 2019 on Great Lakes Symposium on VLSI, 2019

Design of Hardware-Friendly Memory Enhanced Neural Networks.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2019

2017
Vsion: Vehicle Occlusion Handling for Traffic Monitoring.
Proceedings of the International Conference on Video and Image Processing, 2017

2014
Open Domain Continuous Filipino Speech Recognition: Challenges and Baseline Experiments.
IEICE Trans. Inf. Syst., 2014


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