Yang Guo

Orcid: 0000-0001-9050-0866

Affiliations:
  • National University of Defense Technology, Changsha, China


According to our database1, Yang Guo authored at least 104 papers between 2003 and 2024.

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Bibliography

2024
A survey of compute nodes with 100 TFLOPS and beyond for supercomputers.
CCF Trans. High Perform. Comput., June, 2024

A Survey of Design and Optimization for Systolic Array-based DNN Accelerators.
ACM Comput. Surv., January, 2024

Improving the Ability of Thermal Radiation Based Hardware Trojan Detection.
Proceedings of the 33rd USENIX Security Symposium, 2024

Enhancing the PE Utilization for Multi-Precision Systolic Array via Optimizing Computation Latency.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2024

2023
A General Layout Pattern Clustering Using Geometric Matching-based Clip Relocation and Lower-bound Aided Optimization.
ACM Trans. Design Autom. Electr. Syst., November, 2023

A Soft-Error Mitigation Approach Using Pulse Quenching Enhancement at Detailed Placement for Combinational Circuits.
ACM Trans. Design Autom. Electr. Syst., July, 2023

Design of three-factor secure and efficient authentication and key-sharing protocol for IoT devices.
Comput. Commun., April, 2023

2022
Heterogeneous Systolic Array Architecture for Compact CNNs Hardware Accelerators.
IEEE Trans. Parallel Distributed Syst., 2022

A Single-Event Transient Radiation Hardened Low-Dropout Regulator for LC Voltage-Controlled Oscillator.
Symmetry, 2022

MT-3000: a heterogeneous multi-zone processor for HPC.
CCF Trans. High Perform. Comput., 2022

Mentha: Enabling Sparse-Packing Computation on Systolic Arrays.
Proceedings of the 51st International Conference on Parallel Processing, 2022

HCRO-LKSM: A Lightweight Key Sharing and Management Protocol Based on HCRO-PUF for IoT Devices.
Proceedings of the 24th IEEE Int Conf on High Performance Computing & Communications; 8th Int Conf on Data Science & Systems; 20th Int Conf on Smart City; 8th Int Conf on Dependability in Sensor, 2022

Accurate timing prediction at placement stage with look-ahead RC network.
Proceedings of the DAC '22: 59th ACM/IEEE Design Automation Conference, San Francisco, California, USA, July 10, 2022

2021
Configurable Multi-directional Systolic Array Architecture for Convolutional Neural Networks.
ACM Trans. Archit. Code Optim., 2021

Current mirror with charge dissipation transistor for analogue single-event transient mitigation in space application.
IET Circuits Devices Syst., 2021

A New Bidirectional Unsupervised Domain Adaptation Segmentation Framework.
CoRR, 2021

Advancing DSP into HPC, AI, and beyond: challenges, mechanisms, and future directions.
CCF Trans. High Perform. Comput., 2021

A dynamically configurable LFSR-based PUF design against machine learning attacks.
CCF Trans. High Perform. Comput., 2021

Editorial for the special issue on reliability and power efficiency for HPC.
CCF Trans. High Perform. Comput., 2021

A New Bidirectional Unsupervised Domain Adaptation Segmentation Framework.
Proceedings of the Information Processing in Medical Imaging, 2021

Improving Inter-kernel Data Reuse With CTA-Page Coordination in GPGPU.
Proceedings of the IEEE/ACM International Conference On Computer Aided Design, 2021

HeSA: Heterogeneous Systolic Array Architecture for Compact CNNs Hardware Accelerators.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2021

Analysis of Single Events Effects on Supply-Regulated LC-Tank Voltage-Controlled Oscillator.
Proceedings of the 14th IEEE International Conference on ASIC, 2021

2020
Lithography Hotspot Detection with FFT-based Feature Extraction and Imbalanced Learning Rate.
ACM Trans. Design Autom. Electr. Syst., 2020

A Dynamic and Proactive GPU Preemption Mechanism Using Checkpointing.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020

Novel Design Strategy Toward A2 Trojan Detection Based on Built-In Acceleration Structure.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020

AIM: Annealing in Memory for Vision Applications.
Symmetry, 2020

Deviation based clustering for unsupervised person re-identification.
Pattern Recognit. Lett., 2020

Novel probability flipping method for ising annealing chip using circuit unreliability.
Microelectron. J., 2020

Energy clustering for unsupervised person re-identification.
Image Vis. Comput., 2020

Configurable Ring Oscillator PUF Using Hybrid Logic Gates.
IEEE Access, 2020

FIGARO: Improving System Performance via Fine-Grained In-DRAM Data Relocation and Caching.
Proceedings of the 53rd Annual IEEE/ACM International Symposium on Microarchitecture, 2020

A Macro-Micro Weakly-Supervised Framework for AS-OCT Tissue Segmentation.
Proceedings of the Medical Image Computing and Computer Assisted Intervention - MICCAI 2020, 2020

CMSA: Configurable Multi-directional Systolic Array for Convolutional Neural Networks.
Proceedings of the 38th IEEE International Conference on Computer Design, 2020

Maximum Clique Based Method for Optimal Solution of Pattern Classification.
Proceedings of the 38th IEEE International Conference on Computer Design, 2020

Hierarchical Clustering With Hard-Batch Triplet Loss for Person Re-Identification.
Proceedings of the 2020 IEEE/CVF Conference on Computer Vision and Pattern Recognition, 2020

2019
Coordinated DMA: Improving the DRAM Access Efficiency for Matrix Multiplication.
IEEE Trans. Parallel Distributed Syst., 2019

一种基于SAT求解器的组合电路重汇聚现象分析方法 (Reconvergence Phenomena Analysis Method in Combinational Circuits Based on SAT Solver).
计算机科学, 2019

A lightweight and secure-enhanced Strong PUF design on FPGA.
IEICE Electron. Express, 2019

Priority-Based PCIe Scheduling for Multi-Tenant Multi-GPU Systems.
IEEE Comput. Archit. Lett., 2019

28nm Fault-Tolerant Hardening-by-Design Frequency Divider for Reducing Soft Errors in Clock and Data Recovery.
IEEE Access, 2019

A Lightweight LFSR-Based Strong Physical Unclonable Function Design on FPGA.
IEEE Access, 2019

An Efficient Direct Memory Access (DMA) Controller for Scientific Computing Accelerators.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2019

Load-Balanced Link Distribution in Mesh-Based Many-Core Systems.
Proceedings of the 21st IEEE International Conference on High Performance Computing and Communications; 17th IEEE International Conference on Smart City; 5th IEEE International Conference on Data Science and Systems, 2019

Improving the DRAM Access Efficiency for Matrix Multiplication on Multicore Accelerators.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2019

A Framework for Memory Oversubscription Management in Graphics Processing Units.
Proceedings of the Twenty-Fourth International Conference on Architectural Support for Programming Languages and Operating Systems, 2019

2018
An SAT-Based Method to Multithreaded Program Verification for Mobile Crowdsourcing Networks.
Wirel. Commun. Mob. Comput., 2018

Detailed placement for pulse quenching enhancement in anti-radiation combinational circuit design.
Integr., 2018

VP-Router: On balancing the traffic load in on-chip networks.
IEICE Electron. Express, 2018

A task-based multi-core allocation mechanism for packet acceleration.
IEICE Electron. Express, 2018

Cache Access Fairness in 3D Mesh-Based NUCA.
IEEE Access, 2018

Analysis of SET Reconvergence and Hardening in the Combinational Circuit Using a SAT-Based Method.
IEEE Access, 2018

Performance Analysis of Different Convolution Algorithms in GPU Environment.
Proceedings of the 2018 IEEE International Conference on Networking, 2018

Adaptive VC Partitioning for NoCs in GPGPUs.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2018

Accelerating CNNs Using Optimized Scheduling Strategy.
Proceedings of the Algorithms and Architectures for Parallel Processing, 2018

PEP: proactive checkpointing for efficient preemption on GPUs.
Proceedings of the 55th Annual Design Automation Conference, 2018

2017
A Formal Approach to Verify Parameterized Protocols in Mobile Cyber-Physical Systems.
Mob. Inf. Syst., 2017

A novel power-efficient IC test scheme.
IEICE Electron. Express, 2017

A Parallel Test Application Method towards Power Reduction.
J. Electron. Test., 2017

Fairness-oriented switch allocation for networks-on-chip.
Proceedings of the 30th IEEE International System-on-Chip Conference, 2017

Fairness-Oriented and Location-Aware NUCA for Many-Core SoC.
Proceedings of the Eleventh IEEE/ACM International Symposium on Networks-on-Chip, 2017

A Radiation-Immune Low-Jitter High-Frequency PLL for SerDes.
Proceedings of the Computer Engineering and Technology - 21st CCF Conference, 2017

A Mixed-Size Monolithic 3D Placer with 2D Layout Inheritance.
Proceedings of the on Great Lakes Symposium on VLSI 2017, 2017

A radiation hardened low-noise voltage-controlled-oscillator using negative feedback based multipath- current-releasing technology.
Proceedings of the 12th IEEE International Conference on ASIC, 2017

A state recovery design against single-event transient in high-speed phase interpolation clock and data recovery circuit.
Proceedings of the 12th IEEE International Conference on ASIC, 2017

2016
Ripple 2.0: Improved Movement of Cells in Routability-Driven Placement.
ACM Trans. Design Autom. Electr. Syst., 2016

A low-jitter self-biased phase-locked loop for SerDes.
Proceedings of the International SoC Design Conference, 2016

DLL: A dynamic latency-aware load-balancing strategy in 2.5D NoC architecture.
Proceedings of the 34th IEEE International Conference on Computer Design, 2016

Overcoming and Analyzing the Bottleneck of Interposer Network in 2.5D NoC Architecture.
Proceedings of the Advanced Computer Architecture - 11th Conference, 2016

2015
Command-Triggered Microcode Execution for Distributed Shared Memory Based Multi-Core Network-on-Chips.
J. Softw., 2015

Performance Analysis of Homogeneous On-Chip Large-Scale Parallel Computing Architectures for Data-Parallel Applications.
J. Electr. Comput. Eng., 2015

Express Ring: a multi-layer and non-blocking NoC architecture.
IEICE Electron. Express, 2015

Achieving Memory Access Equalization Via Round-Trip Routing Latency Prediction in 3D Many-Core NoCs.
Proceedings of the 2015 IEEE Computer Society Annual Symposium on VLSI, 2015

Equivalence checking of scheduling in high-level synthesis.
Proceedings of the Sixteenth International Symposium on Quality Electronic Design, 2015

An effective analytical 3D placer in monolithic 3D IC designs.
Proceedings of the 2015 IEEE 11th International Conference on ASIC, 2015

2014
An efficient floating-point multiplier for digital signal processors.
IEICE Electron. Express, 2014

Cooperative communication for efficient and scalable all-to-all barrier synchronization on mesh-based many-core NoCs.
IEICE Electron. Express, 2014

A 40nm/65nm process adaptive low jitter phase-locked loop.
Proceedings of the 2014 International Symposium on Integrated Circuits (ISIC), 2014

2013
Efficient translation validation of high-level synthesis.
Proceedings of the International Symposium on Quality Electronic Design, 2013

Translation validation of scheduling in high level synthesis.
Proceedings of the Great Lakes Symposium on VLSI 2013 (part of ECRC), 2013

Application specified soft error failure rate analysis using sequential equivalence checking techniques.
Proceedings of the 18th Asia and South Pacific Design Automation Conference, 2013

An adaptive multi-modulus frequency divider.
Proceedings of the IEEE 10th International Conference on ASIC, 2013

2012
State space reduction in modeling checking parameterized cache coherence protocol by two-dimensional abstraction.
J. Supercomput., 2012

A novel parallel memory organization supporting multiple access types with matched memory modules.
IEICE Electron. Express, 2012

2008
2D Decomposition Sequential Equivalence Checking of System Level and RTL Descriptions.
Proceedings of the 9th International Symposium on Quality of Electronic Design (ISQED 2008), 2008

Explicit Model Checking Based on Integer Pointer and Fibonacci Hash.
Proceedings of the 9th International Conference for Young Computer Scientists, 2008

Efficient Verification of Parameterized Cache Coherence Protocols.
Proceedings of the 9th International Conference for Young Computer Scientists, 2008

2007
Experiences Teaching Functional Verification Techniques with Practical Designs.
Proceedings of the IEEE International Conference on Microelectronic Systems Education, 2007

A Novel Collaborative Verification Environment for SoC Co-Verification.
Proceedings of the 11th International Conference on Computer Supported Cooperative Work in Design, 2007

Coverage Driven Test Generation Framework for RTL Functional Verification.
Proceedings of the 10th International Conference on Computer-Aided Design and Computer Graphics, 2007

2006
Pseudo Share Data Cache in Multiprocessor: PSDMP.
Proceedings of the Frontiers of High Performance Computing and Networking, 2006

TraceDo: An On-Chip Trace System for Real-Time Debug and Optimization in Multiprocessor SoC.
Proceedings of the Parallel and Distributed Processing and Applications, 2006

Scheduling of Transactions Based on Extended Scheduling Timed Petri Nets for SoC System-Level Test-Case Generation.
Proceedings of the Embedded and Ubiquitous Computing, International Conference, 2006

2005
Applying Constraint Logic Programming to Predicate Abstraction of RTL Verilog Descriptions.
Proceedings of the MICAI 2005: Advances in Artificial Intelligence, 2005

MA2TG: A Functional Test Program Generator for Microprocessor Verification.
Proceedings of the Eighth Euromicro Symposium on Digital Systems Design (DSD 2005), 30 August, 2005

Functional Vectors Generation for RT-Level Verilog Descriptions Based on Path Enumeration and Constraint Logic Programming.
Proceedings of the Eighth Euromicro Symposium on Digital Systems Design (DSD 2005), 30 August, 2005

Predicate Abstraction of RTL Verilog Descriptions Using Constraint Logic Programming.
Proceedings of the Automated Technology for Verification and Analysis, 2005

Automatic functional test program generation for microprocessor verification.
Proceedings of the 2005 Conference on Asia South Pacific Design Automation, 2005

2004
Automatic Circuit Extractor for HDL Description Using Program Slicing.
J. Comput. Sci. Technol., 2004

Design and Implementation of a Parallel Verilog Simulator: PVSim.
Proceedings of the 17th International Conference on VLSI Design (VLSI Design 2004), 2004

Assertion-based automated functional vectors generation using constraint logic programming.
Proceedings of the 14th ACM Great Lakes Symposium on VLSI 2004, 2004

CLP Based Static Property Checking.
Proceedings of the Automated Technology for Verification and Analysis: Second International Conference, 2004

Parallel verilog simulation: architecture and circuit partition.
Proceedings of the 2004 Conference on Asia South Pacific Design Automation: Electronic Design and Solution Fair 2004, 2004

2003
An Automatic Circuit Extractor for RTL Verification.
Proceedings of the 12th Asian Test Symposium (ATS 2003), 17-19 November 2003, Xian, China, 2003


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