An Automatic Circuit Extractor for RTL Verification. - Tun Li; Yang Guo 003; Sikun Li (Asian Test Symposium, 2003)

Parallel verilog simulation: architecture and circuit partition. - Tun Li; Yang Guo 003; Sikun Li; Fujiang Ao; Gongjie Li (ASP-DAC, 2004)

CLP Based Static Property Checking. - Tun Li; Yang Guo 003; Sikun Li (ATVA, 2004)

Assertion-based automated functional vectors generation using constraint logic programming. - Tun Li; Yang Guo 003; Sikun Li (ACM Great Lakes Symposium on VLSI, 2004)

Design and Implementation of a Parallel Verilog Simulator: PVSim. - Tun Li; Yang Guo 003; Sikun Li (VLSI Design, 2004)

Automatic Circuit Extractor for HDL Description Using Program Slicing. - Tun Li; Yang Guo 003; Sikun Li (J. Comput. Sci. Technol., 2004)

Automatic functional test program generation for microprocessor verification. - Tun Li; Dan Zhu; Lei Liang; Yang Guo 003; Sikun Li (ASP-DAC, 2005)

Predicate Abstraction of RTL Verilog Descriptions Using Constraint Logic Programming. - Tun Li; Yang Guo 003; Sikun Li; GongJie Liu (ATVA, 2005)

Functional Vectors Generation for RT-Level Verilog Descriptions Based on Path Enumeration and Constraint Logic Programming. - Tun Li; Yang Guo 003; GongJie Liu; Sikun Li (DSD, 2005)

MA2TG: A Functional Test Program Generator for Microprocessor Verification. - Tun Li; Dan Zhu; Yang Guo 003; GongJie Liu; Sikun Li (DSD, 2005)

Applying Constraint Logic Programming to Predicate Abstraction of RTL Verilog Descriptions. - Tun Li; Yang Guo 003; Sikun Li; Dan Zhu (MICAI, 2005)

Scheduling of Transactions Based on Extended Scheduling Timed Petri Nets for SoC System-Level Test-Case Generation. - Jinshan Yu; Tun Li; Yang Guo 003; QingPing Tan (EUC, 2006)

TraceDo: An On-Chip Trace System for Real-Time Debug and Optimization in Multiprocessor SoC. - Xiao Hu 004; Pengyong Ma; Shuming Chen; Yang Guo 003; Xing Fang (ISPA, 2006)

Pseudo Share Data Cache in Multiprocessor: PSDMP. - Pengyong Ma; Xiao Hu 004; Shuming Chen; Yang Guo 003 (ISPA Workshops, 2006)

Coverage Driven Test Generation Framework for RTL Functional Verification. - Yang Guo 003; WanXia Qu; Tun Li; Sikun Li (CAD/Graphics, 2007)

A Novel Collaborative Verification Environment for SoC Co-Verification. - Tun Li; Sikun Li; Jinshan Yu; Yang Guo 003 (CSCWD, 2007)

Experiences Teaching Functional Verification Techniques with Practical Designs. - Tun Li; Yang Guo 003; Sikun Li; Wei Dong; Rangyu Deng (MSE, 2007)

Efficient Verification of Parameterized Cache Coherence Protocols. - Wanxia Qu; Yang Guo 003; Zhengbin Pang; Xiaodong Yang (ICYCS, 2008)

Explicit Model Checking Based on Integer Pointer and Fibonacci Hash. - WanXia Qu; Tun Li; Yang Guo 003; Xiaodong Yang (ICYCS, 2008)

2D Decomposition Sequential Equivalence Checking of System Level and RTL Descriptions. - Dan Zhu; Tun Li; Yang Guo 003; Sikun Li (ISQED, 2008)

A novel parallel memory organization supporting multiple access types with matched memory modules. - Sheng Liu 001; Shuming Chen; Hu Chen; Yang Guo 003 (IEICE Electron. Express, 2012)

State space reduction in modeling checking parameterized cache coherence protocol by two-dimensional abstraction. - Yang Guo 003; WanXia Qu; Long Zhang 004; Weixia Xu (J. Supercomput., 2012)

An adaptive multi-modulus frequency divider. - Hengzhou Yuan; Zhuo Ma; Yang Guo 003 (ASICON, 2013)

Application specified soft error failure rate analysis using sequential equivalence checking techniques. - Tun Li; Dan Zhu; Sikun Li; Yang Guo 003 (ASP-DAC, 2013)

Translation validation of scheduling in high level synthesis. - Tun Li; Yang Guo 003; Wanwei Liu; Mingsheng Tang (ACM Great Lakes Symposium on VLSI, 2013)

Efficient translation validation of high-level synthesis. - Tun Li; Yang Guo 003; Wanwei Liu; Chiyuan Ma (ISQED, 2013)

A 40nm/65nm process adaptive low jitter phase-locked loop. - Hengzhou Yuan; Yang Guo 003; Zhuo Ma (ISIC, 2014)

Cooperative communication for efficient and scalable all-to-all barrier synchronization on mesh-based many-core NoCs. - Xiaowen Chen; Zhonghai Lu; Axel Jantsch; Shuming Chen; Yang Guo 003; Hengzhu Liu (IEICE Electron. Express, 2014)

An efficient floating-point multiplier for digital signal processors. - Zonglin Liu; Sheng Ma; Yang Guo 003 (IEICE Electron. Express, 2014)

An effective analytical 3D placer in monolithic 3D IC designs. - Yande Jiang; Xu He; Chang Liu 019; Yang Guo 003 (ASICON, 2015)

Equivalence checking of scheduling in high-level synthesis. - Tun Li; Jian Hu; Yang Guo 003; Sikun Li; QingPing Tan (ISQED, 2015)

Achieving Memory Access Equalization Via Round-Trip Routing Latency Prediction in 3D Many-Core NoCs. - Xiaowen Chen; Zhonghai Lu; Yang Li; Axel Jantsch; Xueqian Zhao; Shuming Chen; Yang Guo 003; Zonglin Liu; Jianzhuang Lu; Jianghua Wan; Shuwei Sun; Shenggang Chen; et al. (ISVLSI, 2015)

Express Ring: a multi-layer and non-blocking NoC architecture. - Chen Li 015; Sheng Ma; Shenggang Chen; Yang Guo 003; Peng Wang 036 (IEICE Electron. Express, 2015)

Performance Analysis of Homogeneous On-Chip Large-Scale Parallel Computing Architectures for Data-Parallel Applications. - Xiaowen Chen; Zhonghai Lu; Axel Jantsch; Shuming Chen; Yang Guo 003; Shenggang Chen; Hu Chen (J. Electr. Comput. Eng., 2015)

Command-Triggered Microcode Execution for Distributed Shared Memory Based Multi-Core Network-on-Chips. - Xiaowen Chen; Zhonghai Lu; Axel Jantsch; Shuming Chen; Yang Guo 003; Shenggang Chen; Hu Chen; Man Liao (J. Softw., 2015)

Overcoming and Analyzing the Bottleneck of Interposer Network in 2.5D NoC Architecture. - Chen Li 015; Zicong Wang; Lu Wang 019; Sheng Ma; Yang Guo 003 (ACA, 2016)

DLL: A dynamic latency-aware load-balancing strategy in 2.5D NoC architecture. - Chen Li 015; Sheng Ma; Lu Wang 019; Zicong Wang; Xia Zhao 004; Yang Guo 003 (ICCD, 2016)

A low-jitter self-biased phase-locked loop for SerDes. - Hengzhou Yuan; Yang Guo 003; Yao Liu; Bin Liang; Qian-cheng Guo; Jia-wei Tan (ISOCC, 2016)

Ripple 2.0: Improved Movement of Cells in Routability-Driven Placement. - Xu He; Yao Wang 002; Yang Guo 003; Evangeline F. Y. Young (ACM Trans. Design Autom. Electr. Syst., 2016)

A state recovery design against single-event transient in high-speed phase interpolation clock and data recovery circuit. - Jia-wei Tan; Yang Guo 003; Jianjun Chen; Hengzhou Yuan; Xi Chen (ASICON, 2017)

A radiation hardened low-noise voltage-controlled-oscillator using negative feedback based multipath- current-releasing technology. - Hengzhou Yuan; Jianjun Chen; Bin Liang; Yang Guo 003 (ASICON, 2017)

A Mixed-Size Monolithic 3D Placer with 2D Layout Inheritance. - Xu He; Yao Wang 002; Yang Guo 003; Sorin Cotofana (ACM Great Lakes Symposium on VLSI, 2017)

A Radiation-Immune Low-Jitter High-Frequency PLL for SerDes. - Hengzhou Yuan; Jianjun Chen; Bin Liang; Yang Guo 003 (NCCET, 2017)

Fairness-Oriented and Location-Aware NUCA for Many-Core SoC. - Zicong Wang; Xiaowen Chen; Chen Li 015; Yang Guo 003 (NOCS, 2017)

Fairness-oriented switch allocation for networks-on-chip. - Zicong Wang; Xiaowen Chen; Chen Li 015; Yang Guo 003 (SoCC, 2017)

A Parallel Test Application Method towards Power Reduction. - Ding Deng; Yang Guo 003; Zhentao Li (J. Electron. Test., 2017)

A novel power-efficient IC test scheme. - Ding Deng; Xiaowen Chen; Yang Guo 003 (IEICE Electron. Express, 2017)

A Formal Approach to Verify Parameterized Protocols in Mobile Cyber-Physical Systems. - Long Zhang 004; Wenyan Hu; WanXia Qu; Yang Guo 003; Sikun Li (Mob. Inf. Syst., 2017)

PEP: proactive checkpointing for efficient preemption on GPUs. - Chen Li 015; Andrew Zigerelli; Jun Yang 002; Yang Guo 003 (DAC, 2018)

Accelerating CNNs Using Optimized Scheduling Strategy. - Rui Xu; Sheng Ma; Wenwu Li; Yang Guo 003 (ICA3PP (3), 2018)

Adaptive VC Partitioning for NoCs in GPGPUs. - Sheng Ma; Hongyi Lu; Libo Huang; Li Shen 007; Yang Guo 003; Zhiying Wang 003; Wenliang Xue (ISCAS, 2018)

Performance Analysis of Different Convolution Algorithms in GPU Environment. - Rui Xu; Sheng Ma; Yang Guo 003 (NAS, 2018)

Analysis of SET Reconvergence and Hardening in the Combinational Circuit Using a SAT-Based Method. - Chang Liu 019; Long Zhang 004; Xu He; Yang Guo 003 (IEEE Access, 2018)

Cache Access Fairness in 3D Mesh-Based NUCA. - Zicong Wang; Xiaowen Chen; Zhonghai Lu; Yang Guo 003 (IEEE Access, 2018)

A task-based multi-core allocation mechanism for packet acceleration. - Zerun Li; Yang Guo 003; Sheng Liu 001; Junyang Zhang (IEICE Electron. Express, 2018)

VP-Router: On balancing the traffic load in on-chip networks. - Zicong Wang; Xiaowen Chen; Junyang Zhang; Yang Guo 003 (IEICE Electron. Express, 2018)

Detailed placement for pulse quenching enhancement in anti-radiation combinational circuit design. - Chang Liu 019; Xu He; Bin Liang; Yang Guo 003 (Integr., 2018)

An SAT-Based Method to Multithreaded Program Verification for Mobile Crowdsourcing Networks. - Long Zhang 004; WanXia Qu; Yinjia Huo; Yang Guo 003; Sikun Li (Wirel. Commun. Mob. Comput., 2018)

A Framework for Memory Oversubscription Management in Graphics Processing Units. - Chen Li 015; Rachata Ausavarungnirun; Christopher J. Rossbach; Youtao Zhang; Onur Mutlu; Yang Guo 003; Jun Yang 002 (ASPLOS, 2019)

Improving the DRAM Access Efficiency for Matrix Multiplication on Multicore Accelerators. - Sheng Ma; Yang Guo 003; Shenggang Chen; Libo Huang; Zhiying Wang 003 (DATE, 2019)

Load-Balanced Link Distribution in Mesh-Based Many-Core Systems. - Zicong Wang; Xiaowen Chen; Chen Li 015; Yang Guo 003; Man Liao; Zhong Liu (HPCC/SmartCity/DSS, 2019)

An Efficient Direct Memory Access (DMA) Controller for Scientific Computing Accelerators. - Sheng Ma; Libo Huang; Yuanwu Lei; Yang Guo 003; Zhiying Wang 003 (ISCAS, 2019)

A Lightweight LFSR-Based Strong Physical Unclonable Function Design on FPGA. - Shen Hou; Yang Guo 003; Shaoqing Li (IEEE Access, 2019)

28nm Fault-Tolerant Hardening-by-Design Frequency Divider for Reducing Soft Errors in Clock and Data Recovery. - Hengzhou Yuan; Yang Guo 003; Jianjun Chen; Yaqing Chi; Xi Chen; Bin Liang (IEEE Access, 2019)

Priority-Based PCIe Scheduling for Multi-Tenant Multi-GPU Systems. - Chen Li 015; Jun Yang 002; Yifan Sun 002; Lingling Jin; Lingjie Xu; Zheng Cao; Pengfei Fan; David R. Kaeli; Sheng Ma; Yang Guo 003 (IEEE Comput. Archit. Lett., 2019)

A lightweight and secure-enhanced Strong PUF design on FPGA. - Shen Hou; Yang Guo 003; Shaoqing Li; Ding Deng; Yan Lei (IEICE Electron. Express, 2019)

一种基于SAT求解器的组合电路重汇聚现象分析方法 (Reconvergence Phenomena Analysis Method in Combinational Circuits Based on SAT Solver). - Lujie Zhang; Chang Liu 019; Long Zhang 004; Yang Guo 003 (计算机科学, 2019)

Coordinated DMA: Improving the DRAM Access Efficiency for Matrix Multiplication. - Sheng Ma; Zhong Liu; Shenggang Chen; Libo Huang; Yang Guo 003; Zhiying Wang 003; Meidi Zhang (IEEE Trans. Parallel Distributed Syst., 2019)

Hierarchical Clustering With Hard-Batch Triplet Loss for Person Re-Identification. - Kaiwei Zeng; Munan Ning; Yaohua Wang; Yang Guo 003 (CVPR, 2020)

Maximum Clique Based Method for Optimal Solution of Pattern Classification. - Xu He; Yipei Wang; Zhiyong Fu; Yao Wang 002; Yang Guo 003 (ICCD, 2020)

CMSA: Configurable Multi-directional Systolic Array for Convolutional Neural Networks. - Rui Xu; Sheng Ma; Yaohua Wang; Yang Guo 003 (ICCD, 2020)

A Macro-Micro Weakly-Supervised Framework for AS-OCT Tissue Segmentation. - Munan Ning; Cheng Bian; Donghuan Lu; Hong-Yu Zhou; Shuang Yu; Chenglang Yuan; Yang Guo 003; Yaohua Wang; Kai Ma 002; Yefeng Zheng 001 (MICCAI (5), 2020)

FIGARO: Improving System Performance via Fine-Grained In-DRAM Data Relocation and Caching. - Yaohua Wang; Lois Orosa 001; Xiangjun Peng; Yang Guo 003; Saugata Ghose; Minesh Patel; Jeremie S. Kim; Juan Gómez-Luna; Mohammad Sadrosadati; Nika Mansouri-Ghiasi; Onur Mutlu (MICRO, 2020)

Configurable Ring Oscillator PUF Using Hybrid Logic Gates. - Ding Deng; Shen Hou; Zhenyu Wang; Yang Guo 003 (IEEE Access, 2020)

Energy clustering for unsupervised person re-identification. - Kaiwei Zeng; Munan Ning; Yaohua Wang; Yang Guo 003 (Image Vis. Comput., 2020)

Novel probability flipping method for ising annealing chip using circuit unreliability. - Zhi Wang; Yang Guo 003; Jian Zhang 022; Zhao Lv (Microelectron. J., 2020)

Deviation based clustering for unsupervised person re-identification. - Munan Ning; Kaiwei Zeng; Yang Guo 003; Yaohua Wang (Pattern Recognit. Lett., 2020)

AIM: Annealing in Memory for Vision Applications. - Zhi Wang; Xiao Hu 004; Jian Zhang 022; Zhao Lv; Yang Guo 003 (Symmetry, 2020)

Novel Design Strategy Toward A2 Trojan Detection Based on Built-In Acceleration Structure. - Ding Deng; Yaohua Wang; Yang Guo 003 (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020)

A Dynamic and Proactive GPU Preemption Mechanism Using Checkpointing. - Chen Li 015; Andrew Zigerelli; Jun Yang 002; Youtao Zhang; Sheng Ma; Yang Guo 003 (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020)

Lithography Hotspot Detection with FFT-based Feature Extraction and Imbalanced Learning Rate. - Xu He; Yu Deng; Shizhe Zhou; Rui Li 019; Yao Wang 002; Yang Guo 003 (ACM Trans. Design Autom. Electr. Syst., 2020)

Analysis of Single Events Effects on Supply-Regulated LC-Tank Voltage-Controlled Oscillator. - Xi Chen; Qian-cheng Guo; Hengzhou Yuan; Zhenyu Wu; Yang Guo 003 (ASICON, 2021)

HeSA: Heterogeneous Systolic Array Architecture for Compact CNNs Hardware Accelerators. - Rui Xu; Sheng Ma; Yaohua Wang; Yang Guo 003 (DATE, 2021)

Improving Inter-kernel Data Reuse With CTA-Page Coordination in GPGPU. - Xuanyi Li; Chen Li 015; Yang Guo 003; Rachata Ausavarungnirun (ICCAD, 2021)

A New Bidirectional Unsupervised Domain Adaptation Segmentation Framework. - Munan Ning; Cheng Bian; Dong Wei 004; Shuang Yu; Chenglang Yuan; Yaohua Wang; Yang Guo 003; Kai Ma 002; Yefeng Zheng 001 (IPMI, 2021)

Editorial for the special issue on reliability and power efficiency for HPC. - Jifeng He 001; Chenggang Wu 002; Huawei Li 001; Yang Guo 003; Tao Li 022 (CCF Trans. High Perform. Comput., 2021)

A dynamically configurable LFSR-based PUF design against machine learning attacks. - Shen Hou; Ding Deng; Zhenyu Wang; Jiahe Shi; Shaoqing Li; Yang Guo 003 (CCF Trans. High Perform. Comput., 2021)

Advancing DSP into HPC, AI, and beyond: challenges, mechanisms, and future directions. - Yaohua Wang; Chen Li 015; Chang Liu 019; Sheng Liu 001; Yuanwu Lei; Jian Zhang 022; Yang Zhang; Yang Guo 003 (CCF Trans. High Perform. Comput., 2021)

A New Bidirectional Unsupervised Domain Adaptation Segmentation Framework. - Munan Ning; Cheng Bian; Dong Wei 004; Chenglang Yuan; Yaohua Wang; Yang Guo 003; Kai Ma 002; Yefeng Zheng 001 (CoRR, 2021)

Current mirror with charge dissipation transistor for analogue single-event transient mitigation in space application. - Jingtian Liu; Bin Liang; Jianjun Chen; Yaqing Chi; Li Yan; Yang Guo 003 (IET Circuits Devices Syst., 2021)

Configurable Multi-directional Systolic Array Architecture for Convolutional Neural Networks. - Rui Xu; Sheng Ma; Yaohua Wang; Xinhai Chen; Yang Guo 003 (ACM Trans. Archit. Code Optim., 2021)

Accurate timing prediction at placement stage with look-ahead RC network. - Xu He; Zhiyong Fu; Yao Wang 002; Chang Liu 019; Yang Guo 003 (DAC, 2022)

HCRO-LKSM: A Lightweight Key Sharing and Management Protocol Based on HCRO-PUF for IoT Devices. - Zhenyu Wang; Ding Deng; Yang Guo 003; Shaoqing Li (HPCC/DSS/SmartCity/DependSys, 2022)

Mentha: Enabling Sparse-Packing Computation on Systolic Arrays. - Minjin Tang; Mei Wen; Yasong Cao; Junzhong Shen; Jianchao Yang; Jiawei Fei; Yang Guo 003; Sheng Liu 001 (ICPP, 2022)

MT-3000: a heterogeneous multi-zone processor for HPC. - Kai Lu; Yaohua Wang; Yang Guo 003; Chun Huang; Sheng Liu 001; Ruibo Wang; Jianbin Fang; Tao Tang 001; Zhaoyun Chen; Biwei Liu; Zhong Liu; Yuanwu Lei; et al. (CCF Trans. High Perform. Comput., 2022)

A Single-Event Transient Radiation Hardened Low-Dropout Regulator for LC Voltage-Controlled Oscillator. - Xi Chen; Qian-cheng Guo; Hengzhou Yuan; Yang Guo 003 (Symmetry, 2022)

Heterogeneous Systolic Array Architecture for Compact CNNs Hardware Accelerators. - Rui Xu; Sheng Ma; Yaohua Wang; Yang Guo 003; Dongsheng Li 001; Yuran Qiao (IEEE Trans. Parallel Distributed Syst., 2022)

Design of three-factor secure and efficient authentication and key-sharing protocol for IoT devices. - Zhenyu Wang; Ding Deng; Shen Hou; Yang Guo 003; Shaoqing Li (Comput. Commun., 2023)

A Soft-Error Mitigation Approach Using Pulse Quenching Enhancement at Detailed Placement for Combinational Circuits. - Xu He; Yao Wang 002; Chang Liu 019; Qiang Wu; Juan Luo; Yang Guo 003 (ACM Trans. Design Autom. Electr. Syst., 2023)

A General Layout Pattern Clustering Using Geometric Matching-based Clip Relocation and Lower-bound Aided Optimization. - Xu He; Yao Wang 002; Zhiyong Fu; Yipei Wang; Yang Guo 003 (ACM Trans. Design Autom. Electr. Syst., 2023)

Enhancing the PE Utilization for Multi-Precision Systolic Array via Optimizing Computation Latency. - Jing Feng; Mei Wen; Xin Ju; Junzhong Shen; Yang Guo 003 (ISCAS, 2024)

Improving the Ability of Thermal Radiation Based Hardware Trojan Detection. - Ting Su 009; Yaohua Wang; Shi Xu; Lusi Zhang; Simin Feng; Jialong Song; Yiming Liu; Yongkang Tang; Yang Zhang; Shaoqing Li; Yang Guo 003; Hengzhu Liu (USENIX Security Symposium, 2024)

A Survey of Design and Optimization for Systolic Array-based DNN Accelerators. - Rui Xu; Sheng Ma; Yang Guo 003; Dongsheng Li 001 (ACM Comput. Surv., 2024)

A survey of compute nodes with 100 TFLOPS and beyond for supercomputers. - Junsheng Chang; Kai Lu; Yang Guo 003; Yongwen Wang; Zhenyu Zhao; Libo Huang; Hongwei Zhou; Yao Wang 002; Fei Lei; Biwei Zhang (CCF Trans. High Perform. Comput., 2024)