Peng Chen
Orcid: 0000-0002-2872-9421Affiliations:
- University College Dublin, School of Electrical and Electronic Engineering, Ireland
- Delft University of Technology, The Netherlands (former)
According to our database1,
Peng Chen
authored at least 16 papers
between 2015 and 2023.
Collaborative distances:
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Bibliography
2023
Analysis and Design of a 15.2-to-18.2-GHz Inverse-Class-F VCO With a Balanced Dual-Core Topology Suppressing the Flicker Noise Upconversion.
IEEE Trans. Circuits Syst. I Regul. Pap., December, 2023
IEEE J. Solid State Circuits, 2023
2022
IEEE Trans. Circuits Syst. I Regul. Pap., 2022
A 529-μW Fractional-N All-Digital PLL Using TDC Gain Auto-Calibration and an Inverse-Class-F DCO in 65-nm CMOS.
IEEE Trans. Circuits Syst. I Regul. Pap., 2022
A 2.6-to-4.1GHz Fractional-N Digital PLL Based on a Time-Mode Arithmetic Unit Achieving -249.4dB FoM and -59dBc Fractional Spurs.
Proceedings of the IEEE International Solid-State Circuits Conference, 2022
2021
IEEE Trans. Circuits Syst. I Regul. Pap., 2021
IEEE Trans. Circuits Syst. I Regul. Pap., 2021
A Feedforward and Feedback Constant-Slope Digital-to-Time Converter in 28nm CMOS Achieving ≤ 0.12% INL/Range over >100mV Supply Range.
Proceedings of the 2021 Symposium on VLSI Circuits, Kyoto, Japan, June 13-19, 2021, 2021
2019
A Low-Noise Fractional- ${N}$ Digital Frequency Synthesizer With Implicit Frequency Tripling for mm-Wave Applications.
IEEE J. Solid State Circuits, 2019
A 31-µW, 148-fs Step, 9-bit Capacitor-DAC-Based Constant-Slope Digital-to-Time Converter in 28-nm CMOS.
IEEE J. Solid State Circuits, 2019
2018
An On-Chip Self-Characterization of a Digital-to-Time Converter by Embedding it in a First-Order ΔΣ Loop.
IEEE Trans. Circuits Syst. I Regul. Pap., 2018
2017
A 15-μW, 103-fs step, 5-bit capacitor-DAC-based constant-slope digital-to-time converter in 28nm CMOS.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2017
2016
Proceedings of the Second International Conference on Event-based Control, 2016
2015
Proceedings of the 2015 IEEE International Symposium on Circuits and Systems, 2015
Design and built-in characterization of digital-to-time converters for ultra-low power ADPLLs.
Proceedings of the ESSCIRC Conference 2015, 2015