Design and built-in characterization of digital-to-time converters for ultra-low power ADPLLs. - Peng Chen 022; Xiongchuan Huang; Yao-Hong Liu; Ming Ding 003; Cui Zhou; Ao Ba; Kathleen Philips; Harmke de Groot; Robert Bogdan Staszewski (ESSCIRC, 2015)

Fractional spur suppression in all-digital phase-locked loops. - Peng Chen 022; Xiongchuan Huang; Robert Bogdan Staszewski (ISCAS, 2015)

Exponential extended flash time-to-digital converter. - Peng Chen 022; Robert Bogdan Staszewski (EBCCSP, 2016)

A 15-μW, 103-fs step, 5-bit capacitor-DAC-based constant-slope digital-to-time converter in 28nm CMOS. - Peng Chen 022; Feifei Zhang; Zhirui Zong; Hao Zheng; Teerachot Siriburanon; Robert Bogdan Staszewski (A-SSCC, 2017)

An On-Chip Self-Characterization of a Digital-to-Time Converter by Embedding it in a First-Order ΔΣ Loop. - Peng Chen 022; Xiongchuan Huang; Yue Chen; Lianbo Wu; Robert Bogdan Staszewski (IEEE Trans. Circuits Syst. I Regul. Pap., 2018)

A 31-µW, 148-fs Step, 9-bit Capacitor-DAC-Based Constant-Slope Digital-to-Time Converter in 28-nm CMOS. - Peng Chen 022; Feifei Zhang; Zhirui Zong; Suoping Hu; Teerachot Siriburanon; Robert Bogdan Staszewski (IEEE J. Solid State Circuits, 2019)

A Low-Noise Fractional- ${N}$ Digital Frequency Synthesizer With Implicit Frequency Tripling for mm-Wave Applications. - Zhirui Zong; Peng Chen 022; Robert Bogdan Staszewski (IEEE J. Solid State Circuits, 2019)

A Feedforward and Feedback Constant-Slope Digital-to-Time Converter in 28nm CMOS Achieving ≤ 0.12% INL/Range over >100mV Supply Range. - Peng Chen 022; Feifei Zhang; Suoping Hu; Robert Bogdan Staszewski (VLSI Circuits, 2021)

A Type-II Phase-Tracking Receiver. - Suoping Hu; Jianglin Du; Peng Chen 022; Hieu Minh Nguyen; Philip Quinlan; Teerachot Siriburanon; Robert Bogdan Staszewski (IEEE J. Solid State Circuits, 2021)

A 0.7-V Sub-mW Type-II Phase-Tracking Bluetooth Low Energy Receiver in 28-nm CMOS. - Suoping Hu; Peng Chen 022; Philip Quinlan; Robert Bogdan Staszewski (IEEE Trans. Circuits Syst. I Regul. Pap., 2021)

An Active-Under-Coil RFDAC With Analog Linear Interpolation in 28-nm CMOS. - Feifei Zhang; Peng Chen 022; Jeffrey S. Walling; Anding Zhu; Robert Bogdan Staszewski (IEEE Trans. Circuits Syst. I Regul. Pap., 2021)

A 2.6-to-4.1GHz Fractional-N Digital PLL Based on a Time-Mode Arithmetic Unit Achieving -249.4dB FoM and -59dBc Fractional Spurs. - Zhong Gao; Jingchu He; Martin Fritz; Jiang Gong; Yiyu Shen; Zhirui Zong; Peng Chen 022; Gerd Spalink; Ben Eitel; Ken Yamamoto; Robert Bogdan Staszewski; Morteza S. Alavi; et al. (ISSCC, 2022)

A 529-μW Fractional-N All-Digital PLL Using TDC Gain Auto-Calibration and an Inverse-Class-F DCO in 65-nm CMOS. - Peng Chen 022; Xi Meng; Jun Yin 001; Pui-In Mak; Rui Paulo Martins; Robert Bogdan Staszewski (IEEE Trans. Circuits Syst. I Regul. Pap., 2022)

Mismatch Analysis of DTCs With an Improved BIST-TDC in 28-nm CMOS. - Peng Chen 022; Jun Yin 001; Feifei Zhang; Pui-In Mak; Rui Paulo Martins; Robert Bogdan Staszewski (IEEE Trans. Circuits Syst. I Regul. Pap., 2022)

A Low-Spur Fractional-N PLL Based on a Time-Mode Arithmetic Unit. - Zhong Gao; Jingchu He; Martin Fritz; Jiang Gong; Yiyu Shen; Zhirui Zong; Peng Chen 022; Gerd Spalink; Ben Eitel; Morteza S. Alavi; Robert Bogdan Staszewski; Masoud Babaie (IEEE J. Solid State Circuits, 2023)

Analysis and Design of a 15.2-to-18.2-GHz Inverse-Class-F VCO With a Balanced Dual-Core Topology Suppressing the Flicker Noise Upconversion. - Xi Meng; Haoran Li; Peng Chen 022; Jun Yin 001; Pui-In Mak; Rui Paulo Martins (IEEE Trans. Circuits Syst. I Regul. Pap., 2023)