Ziran Zhu

Orcid: 0000-0002-9475-6364

According to our database1, Ziran Zhu authored at least 31 papers between 2017 and 2024.

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Bibliography

2024
High-Performance 3-D Placement Engine With Physical-Aware Incremental Partitioning.
IEEE Trans. Circuits Syst. II Express Briefs, March, 2024

High-Performance Placement Engine for Modern Large-Scale FPGAs With Heterogeneity and Clock Constraints.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., March, 2024

An Effective Routing Refinement Algorithm Based on Incremental Replacement and Rerouting.
IEEE Trans. Circuits Syst. II Express Briefs, January, 2024

An effective routability-driven packing algorithm for large-scale heterogeneous FPGAs.
Integr., January, 2024

Consistency Models Improve Diffusion Inverse Solvers.
CoRR, 2024

Noise Dimension of GAN: An Image Compression Perspective.
CoRR, 2024

Idempotence and Perceptual Image Compression.
CoRR, 2024

2023
Variational Label-Correlation Enhancement for Congestion Prediction.
CoRR, 2023

A Hybrid Reinforcement Learning and Genetic Algorithm for VLSI Floorplanning.
Proceedings of the 15th International Conference on Machine Learning and Computing, 2023

Disjoint-Path and Golden-Pin Based Irregular PCB Routing with Complex Constraints.
Proceedings of the 60th ACM/IEEE Design Automation Conference, 2023

Efficient Global Optimization for Large Scaled Ordered Escape Routing.
Proceedings of the 28th Asia and South Pacific Design Automation Conference, 2023

2022
Mixed-Cell-Height Placement With Drain-to-Drain Abutment and Region Constraints.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022

Novel Proximal Group ADMM for Placement Considering Fogging and Proximity Effects.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022

Timing-Aware Fill Insertions With Design-Rule and Density Constraints.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022

A Robust Global Routing Engine with High-Accuracy Cell Movement under Advanced Constraints.
Proceedings of the 41st IEEE/ACM International Conference on Computer-Aided Design, 2022

High-performance placement for large-scale heterogeneous FPGAs with clock constraints.
Proceedings of the DAC '22: 59th ACM/IEEE Design Automation Conference, San Francisco, California, USA, July 10, 2022

Subgraph matching based reference placement for PCB designs: late breaking results.
Proceedings of the DAC '22: 59th ACM/IEEE Design Automation Conference, San Francisco, California, USA, July 10, 2022

Voronoi Diagram Based Heterogeneous Circuit Layout Centerline Extraction for Mask Verification.
Proceedings of the 27th Asia and South Pacific Design Automation Conference, 2022

2021
A Robust Modulus-Based Matrix Splitting Iteration Method for Mixed-Cell-Height Circuit Legalization.
ACM Trans. Design Autom. Electr. Syst., 2021

Topology-Aware Bus Routing in Complex Networks of Very-Large-Scale Integration with Nonuniform Track Configurations and Obstacles.
Complex., 2021

Late Breaking Results: Heterogeneous Circuit Layout Centerline Extraction for Mask Verification.
Proceedings of the 58th ACM/IEEE Design Automation Conference, 2021

Late Breaking Results: An Effective Legalization Algorithm for Heterogeneous FPGAs with Complex Constraints.
Proceedings of the 58th ACM/IEEE Design Automation Conference, 2021

2020
Mixed-Cell-Height Legalization Considering Technology and Region Constraints.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020

Mixed-cell-height legalization considering complex minimum width constraints and half-row fragmentation effect.
Integr., 2020

An Improved Simulated Annealing Algorithm With Excessive Length Penalty for Fixed-Outline Floorplanning.
IEEE Access, 2020

Hamiltonian Path Based Mixed-Cell-Height Legalization for Neighbor Diffusion Effect Mitigation.
Proceedings of the 57th ACM/IEEE Design Automation Conference, 2020

2018
Mixed-cell-height legalization considering technology and region constraints.
Proceedings of the International Conference on Computer-Aided Design, 2018

Generalized augmented lagrangian and its applications to VLSI global placement.
Proceedings of the 55th Annual Design Automation Conference, 2018

2017
Discrete Relaxation Method for Triple Patterning Lithography Layout Decomposition.
IEEE Trans. Computers, 2017

An adaptive hybrid memetic algorithm for thermal-aware non-slicing VLSI floorplanning.
Integr., 2017

Toward Optimal Legalization for Mixed-Cell-Height Circuit Designs.
Proceedings of the 54th Annual Design Automation Conference, 2017


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