Zhong Wang

Affiliations:
  • University of Notre Dame, Department of Computer Science and Engineering, Notre Dame IN, USA (PhD 2007)


According to our database1, Zhong Wang authored at least 10 papers between 2000 and 2005.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

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Bibliography

2005
Energy-aware variable partitioning and instruction scheduling for multibank memory architectures.
ACM Trans. Design Autom. Electr. Syst., 2005

2004
Power Aware Variable Partitioning and Instruction Scheduling for Multiple Memory Banks.
Proceedings of the 2004 Design, 2004

2003
Register aware scheduling for distributed cache clustered architecture.
Proceedings of the 2003 Asia and South Pacific Design Automation Conference, 2003

2002
Partitioning and Scheduling DSP Applications with Maximal Memory Access Hiding.
EURASIP J. Adv. Signal Process., 2002

2001
Minimizing Average Schedule Length under Memory Constraints by Optimal Partitioning and Prefetching.
J. VLSI Signal Process., 2001

Optimal loop scheduling for hiding memory latency based on two-level partitioning and prefetching.
IEEE Trans. Signal Process., 2001

Scheduling and partitioning for multiple loop nests.
Proceedings of the 14th International Symposium on Systems Synthesis, 2001

Optimal partitioning and balanced scheduling with the maximal overlap of data footprints.
Proceedings of the 11th ACM Great Lakes Symposium on VLSI 2001, 2001

Combined partitioning and data padding for scheduling multiple loop nests.
Proceedings of the 2001 International Conference on Compilers, 2001

2000
Optimal two level partitioning and loop scheduling for hiding memory latency for DSP applications.
Proceedings of the 37th Conference on Design Automation, 2000


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