Yunhui Qiu

Orcid: 0000-0003-2754-6655

According to our database1, Yunhui Qiu authored at least 16 papers between 2018 and 2024.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

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Bibliography

2024
HETA: A Heterogeneous Temporal CGRA Modeling and Design Space Exploration via Bayesian Optimization.
IEEE Trans. Very Large Scale Integr. Syst., March, 2024

FDRA: A Framework for a Dynamically Reconfigurable Accelerator Supporting Multi-Level Parallelism.
ACM Trans. Reconfigurable Technol. Syst., March, 2024

2023
THRAM: A Template-based Heterogeneous CGRA Modeling Framework Supporting Fast DSE.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2023

A Dynamic Partial Reconfigurable CGRA Framework for Multi-Kernel Applications.
Proceedings of the International Conference on Field Programmable Technology, 2023

E<sup>2</sup>-ACE: An Energy-Efficient Reconfigurable Crypto-Accelerator with Agile End-to-End Toolchain.
Proceedings of the International Conference on Field Programmable Technology, 2023

PRAD: A Bayesian Optimization-based DSE Framework for Parameterized Reconfigurable Architecture Design.
Proceedings of the 31st IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, 2023

UPTRA: An Ultra-Parameterized Temporal CGRA Modeling and Optimization.
Proceedings of the 31st IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, 2023

An Automatic Optimization Method of Combinational Logic Loops in CGRA.
Proceedings of the 15th IEEE International Conference on ASIC, 2023

2022
A High-Performance and Scalable NVMe Controller Featuring Hardware Acceleration.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022

TRAM: An Open-Source Template-based Reconfigurable Architecture Modeling Framework.
Proceedings of the 32nd International Conference on Field-Programmable Logic and Applications, 2022

2021
A High-performance Open-channel Open-way NAND Flash Controller Architecture.
Proceedings of the 31st International Conference on Field-Programmable Logic and Applications, 2021

2020
FULL-KV: Flexible and Ultra-Low-Latency In-Memory Key-Value Store System Design on CPU-FPGA.
IEEE Trans. Parallel Distributed Syst., 2020

High Throughput and Low Latency Multi-Version Management Key-Value Storage Accelerator.
Proceedings of the International Conference on Field-Programmable Technology, 2020

2019
High-Throughput and Low-Latency Distributed Management Proxy for Key-Value Store Over 100Gbps Ethernet on FPGA.
Proceedings of the International Conference on Field-Programmable Technology, 2019

A Low-Latency Multi-Version Key-Value Store Using B-Tree on an FPGA-CPU Platform.
Proceedings of the 29th International Conference on Field Programmable Logic and Applications, 2019

2018
Ultra-Low-Latency and Flexible In-memory Key-Value Store System Design on CPU-FPGA.
Proceedings of the International Conference on Field-Programmable Technology, 2018


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