Young Jun Park
According to our database1,
Young Jun Park
authored at least 18 papers
between 2014 and 2023.
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Bibliography
2023
A 192-Gb 12-High 896-GB/s HBM3 DRAM With a TSV Auto-Calibration Scheme and Machine-Learning-Based Layout Optimization.
IEEE J. Solid State Circuits, 2023
2022
A 192-Gb 12-High 896-GB/s HBM3 DRAM with a TSV Auto-Calibration Scheme and Machine-Learning-Based Layout Optimization.
Proceedings of the IEEE International Solid-State Circuits Conference, 2022
2020
Convolutional neural network-based safety evaluation method for structures with dynamic responses.
Expert Syst. Appl., 2020
22.3 A 128Gb 8-High 512GB/s HBM2E DRAM with a Pseudo Quarter Bank Structure, Power Dispersion and an Instruction-Based At-Speed PMBIST.
Proceedings of the 2020 IEEE International Solid- State Circuits Conference, 2020
2018
All-digital ΔΣ time-to-digital converter with Bi-Directional gated delay line time integrator.
Microelectron. J., 2018
2017
All-digital ΔΣ TDC with differential bi-directional gated-delay-line time integrator.
Proceedings of the IEEE 60th International Midwest Symposium on Circuits and Systems, 2017
Proceedings of the IEEE 60th International Midwest Symposium on Circuits and Systems, 2017
Proceedings of the IEEE 60th International Midwest Symposium on Circuits and Systems, 2017
Proceedings of the International SoC Design Conference, 2017
A high-efficiency active rectifier by using zero current sensing and deglitch circuit for inductive coupling receiver.
Proceedings of the International SoC Design Conference, 2017
6-Parallel RF energy harvesting rectifier with high power conversion efficiency (PCE) for 5.8GHz 3W wireless power transfer.
Proceedings of the International SoC Design Conference, 2017
2016
Proceedings of the IEEE International Symposium on Circuits and Systems, 2016
Proceedings of the IEEE International Symposium on Circuits and Systems, 2016
2015
Proceedings of the 12th International Conference on Ubiquitous Robots and Ambient Intelligence, 2015
A 12.88 MS/s 0.28 pJ/conv.step 8-bit stage-interleaved pulse-shrinking time-to-digital converter in 130 nm CMOS.
Proceedings of the IEEE 58th International Midwest Symposium on Circuits and Systems, 2015
0.25-4 ns 185 MS/s 4-bit pulse-shrinking time-to-digital converter in 130 nm CMOS using a 2-step conversion scheme.
Proceedings of the IEEE 58th International Midwest Symposium on Circuits and Systems, 2015
2014
25.2 A 1.2V 8Gb 8-channel 128GB/s high-bandwidth memory (HBM) stacked DRAM with effective microbump I/O test methods using 29nm process and TSV.
Proceedings of the 2014 IEEE International Conference on Solid-State Circuits Conference, 2014