Yong Lim

According to our database1, Yong Lim authored at least 22 papers between 1985 and 2024.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

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Bibliography

2024
A Fully Integrated, Low-Noise, Cost-Effective Single-Crystal-Oscillator-Based Clock Management IC in 28-nm CMOS.
IEEE J. Solid State Circuits, June, 2024

9.2 A 2.08mW 64.4dB SNDR 400MS/s 12b Pipelined-SAR ADC using Mismatch and PVT Variation Tolerant Dynamically Biased Ring Amplifier in 8nm.
Proceedings of the IEEE International Solid-State Circuits Conference, 2024

9.6 A 6<sup>th</sup>-Order Quadrature CTDSM using Double-OTA and Quadrature NSSAR with 171.3dB FoMs in 14nm.
Proceedings of the IEEE International Solid-State Circuits Conference, 2024

2023
A 243μW 97.4dB-DR 50kHz-BW Multi-Rate CT Zoom ADC with Inherent DAC Mismatch Tolerance.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2023

SQuARe: A Large-Scale Dataset of Sensitive Questions and Acceptable Responses Created through Human-Machine Collaboration.
Proceedings of the 61st Annual Meeting of the Association for Computational Linguistics (Volume 1: Long Papers), 2023

2022
A Single Path Digital-IF Receiver Supporting Inter/Intra 5-CA With a Single Integer LO-PLL in 14-nm CMOS FinFET.
IEEE J. Solid State Circuits, 2022

A 0.56mW 63.6dB SNDR 250MS/s SAR ADC in 8nm FinFET.
Proceedings of the IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits 2022), 2022

A Single-Path Digital-IF Receiver Supporting Inter/Intra 5-CA with a Single Integer LO-PLL in 14nm CMOS FinFET.
Proceedings of the IEEE International Solid-State Circuits Conference, 2022

A Single-Crystal-Oscillator-Based Clock-Management IC with 18× Start-Up Time Reduction and 0.68ppm/ºC Duty-Cycled Machine-Learning-Based RCO Calibration.
Proceedings of the IEEE International Solid-State Circuits Conference, 2022

A Pipeline ADC with Negative C-assisted SC Amplifier Canceling Gain Error and Nonlinearity.
Proceedings of the 48th IEEE European Solid State Circuits Conference, 2022

Data Governance and Trust: Lessons from South Korean Experiences Coping with COVID-19.
Proceedings of the Cambridge Handbook of Responsible Artificial Intelligence, 2022

2021
10.1 A 116μ W 104.4dB-DR 100.6dB-SNDR CT Δ∑ Audio ADC Using Tri-Level Current-Steering DAC with Gate-Leakage Compensated Off-Transistor-Based Bias Noise Filter.
Proceedings of the IEEE International Solid-State Circuits Conference, 2021

2020
An Effective Transconductance Controlled Offset Calibration for Dynamic Comparators.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2020

2019
A Blocker-Tolerant Direct Sampling Receiver for Wireless Multi-Channel Communication in 14nm FinFET CMOS.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2019

2017
A 1.5-GHz 6.144T Correlations/s 64 × 64 Cross-Correlator With 128 Integrated ADCs for Real-Time Synthetic Aperture Imaging.
IEEE J. Solid State Circuits, 2017

2016
A 16-channel noise-shaping machine learning analog-digital interface.
Proceedings of the 2016 IEEE Symposium on VLSI Circuits, 2016

2015
A 1 mW 71.5 dB SNDR 50 MS/s 13 bit Fully Differential Ring Amplifier Based SAR-Assisted Pipeline ADC.
IEEE J. Solid State Circuits, 2015

A 100 MS/s, 10.5 Bit, 2.46 mW Comparator-Less Pipeline ADC Using Self-Biased Ring Amplifiers.
IEEE J. Solid State Circuits, 2015

26.1 A 1mW 71.5dB SNDR 50MS/S 13b fully differential ring-amplifier-based SAR-assisted pipeline ADC.
Proceedings of the 2015 IEEE International Solid-State Circuits Conference, 2015

2014
11.5 A 100MS/s 10.5b 2.46mW comparator-less pipeline ADC using self-biased ring amplifiers.
Proceedings of the 2014 IEEE International Conference on Solid-State Circuits Conference, 2014

2010
A 1.1e- temporal noise 1/3.2-inch 8Mpixel CMOS image sensor using pseudo-multiple sampling.
Proceedings of the IEEE International Solid-State Circuits Conference, 2010

1985
An interpolation technique for computing the DFT of a sparse sequence.
IEEE Trans. Acoust. Speech Signal Process., 1985


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