Yizhe Hu
Orcid: 0000-0003-3685-7666
According to our database1,
Yizhe Hu
authored at least 18 papers
between 2013 and 2023.
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Bibliography
2023
A 30-GHz Class-F Quadrature DCO Using Phase Shifts Between Drain-Gate-Source for Low Flicker Phase Noise and I/Q Exactness.
IEEE J. Solid State Circuits, 2023
An 18.8-to-23.3 GHz ADPLL Based on Charge-Steering-Sampling Technique Achieving 75.9 fs RMS Jitter and -252 dB FoM.
Proceedings of the 2023 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits), 2023
2022
IEEE Trans. Circuits Syst. II Express Briefs, 2022
Flicker Phase-Noise Reduction Using Gate-Drain Phase Shift in Transformer-Based Oscillators.
IEEE Trans. Circuits Syst. I Regul. Pap., 2022
A Charge-Sharing Locking Technique With a General Phase Noise Theory of Injection Locking.
IEEE J. Solid State Circuits, 2022
A Compact 0.2-0.3-V Inverse-Class-F<sub>23</sub> Oscillator for Low 1/f<sup>3</sup> Noise Over Wide Tuning Range.
IEEE J. Solid State Circuits, 2022
2021
IEEE Trans. Circuits Syst. II Express Briefs, 2021
IEEE J. Solid State Circuits, 2021
Proceedings of the 2021 Symposium on VLSI Circuits, Kyoto, Japan, June 13-19, 2021, 2021
2020
17.6 A 21.7-to-26.5GHz Charge-Sharing Locking Quadrature PLL with Implicit Digital Frequency-Tracking Loop Achieving 75fs Jitter and -250dB FoM.
Proceedings of the 2020 IEEE International Solid- State Circuits Conference, 2020
2019
Intuitive Understanding of Flicker Noise Reduction via Narrowing of Conduction Angle in Voltage-Biased Oscillators.
IEEE Trans. Circuits Syst. II Express Briefs, 2019
28 GHz Quadrature Frequency Generation Exploiting Injection-Locked Harmonic Extractors for 5G Communications.
Proceedings of the 17th IEEE International New Circuits and Systems Conference, 2019
A 0.3V, 35% Tuning-Range, 60kHz 1/f<sup>3</sup>-Corner Digitally Controlled Oscillator with Vertically Integrated Switched Capacitor Banks Achieving FoMT of -199dB in 28-nm CMOS.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2019
DTC-Assisted All-Digital Phase-Locked Loop Exploiting Hybrid Time/Voltage Phase Digitization.
Proceedings of the 2019 IEEE Asia Pacific Conference on Circuits and Systems, 2019
2018
A Low-Flicker-Noise 30-GHz Class-F<sub>23</sub> Oscillator in 28-nm CMOS Using Implicit Resonance and Explicit Common-Mode Return Path.
IEEE J. Solid State Circuits, 2018
2017
A 30-GHz class-F23 oscillator in 28nm CMOS using harmonic extraction and achieving 120 kHz 1/f<sup>3</sup> corner.
Proceedings of the 43rd IEEE European Solid State Circuits Conference, 2017
2015
A modeling approach for mixed-mode FMCW synthesizer allowing frequency error analysis.
Proceedings of the 2015 IEEE International Symposium on Circuits and Systems, 2015
2013
J. Circuits Syst. Comput., 2013