Yijie Wei

Orcid: 0000-0001-7223-0495

According to our database1, Yijie Wei authored at least 13 papers between 2020 and 2024.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

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PhD thesis 
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Links

On csauthors.net:

Bibliography

2024
Blockchain-based collaborative business process data sharing and access control.
J. Reliab. Intell. Environ., March, 2024

33.2 A Sub-1μJ/class Headset-Integrated Mind Imagery and Control SoC for VR/MR Applications with Teacher-Student CNN and General-Purpose Instruction Set Architecture.
Proceedings of the IEEE International Solid-State Circuits Conference, 2024

2023
Tuning to Real for Single-Spectrum Hyperspectral Target Detection.
Proceedings of the 13th Workshop on Hyperspectral Imaging and Signal Processing: Evolution in Remote Sensing, 2023

Human Activity Recognition SoC for AR/VR with Integrated Neural Sensing, AI Classifier and Chained Infrared Communication for Multi-chip Collaboration.
Proceedings of the 2023 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits), 2023

A General-Purpose Compute-in-Memory Processor Combining CPU and Deep Learning with Elevated CPU Efficiency and Enhanced Data Locality.
Proceedings of the 2023 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits), 2023

MTQ-Caps: A Multi-task Capsule Network for Blind Image Quality Assessment.
Proceedings of the Pattern Recognition and Computer Vision - 6th Chinese Conference, 2023

2022
Human emotion based real-time memory and computation management on resource-limited edge devices.
Proceedings of the DAC '22: 59th ACM/IEEE Design Automation Conference, San Francisco, California, USA, July 10, 2022

A 65nm Implantable Gesture Classification SoC for Rehabilitation with Enhanced Data Compression and Encoding for Robust Neural Network Operation Under Wireless Power Condition.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2022

2021
A Gesture Classification SoC for Rehabilitation With ADC-Less Mixed-Signal Feature Extraction and Training Capable Neural Network Classifier.
IEEE J. Solid State Circuits, 2021

2020
An Adaptive Clock Scheme Exploiting Instruction-Based Dynamic Timing Slack for a GPGPU Architecture.
IEEE J. Solid State Circuits, 2020

A Wearable Bio-signal Processing System with Ultra-low-power SoC and Collaborative Neural Network Classifier for Low Dimensional Data Communication.
Proceedings of the 42nd Annual International Conference of the IEEE Engineering in Medicine & Biology Society, 2020

Exploration of Design Space and Runtime Optimization for Affective Computing in Machine Learning Empowered Ultra-Low Power SoC.
Proceedings of the 57th ACM/IEEE Design Automation Conference, 2020

A Fully-integrated Gesture and Gait Processing SoC for Rehabilitation with ADC-less Mixed-signal Feature Extraction and Deep Neural Network for Classification and Online Training.
Proceedings of the 2020 IEEE Custom Integrated Circuits Conference, 2020


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