Xin-Yu Shih
Orcid: 0000-0002-9045-5847
According to our database1,
Xin-Yu Shih
authored at least 32 papers
between 2008 and 2024.
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Bibliography
2024
High-Area-Efficiency Polar Decoder Chip Architecture Reconfiguring SCL-Decoding With Reconfigurable Pipelined Sorter and SCF-Decoding With Non-Uniform 4-Segment CRC.
IEEE Trans. Circuits Syst. II Express Briefs, April, 2024
2023
Design and Implementation of Dual-Mode Support Vector Machine (SVM) Trainer and Classifier Chip Architecture for Human Disease Detection Applications.
IEEE Trans. Circuits Syst. I Regul. Pap., December, 2023
Unified chip hardware architecture of KD-tree mean-based trainer and speeding-up classifier with repeat-point searching for various applications.
Integr., November, 2023
Design and Implementation of Decision-Tree (DT) Online Training Hardware Using Divider-Free GI Calculation and Speeding-Up Double-Root Classifier.
IEEE Trans. Circuits Syst. I Regul. Pap., February, 2023
Low-Cost Hardware Design of Fast 3D-Sorter Engine for Successive Cancellation List Polar-Decoders in 5G Applications.
Proceedings of the International Conference on Consumer Electronics - Taiwan, 2023
2022
Reconfigurable Hardware Architecture of Area-Efficient Multimode Successive Cancellation (SC) Decoder.
IEEE Trans. Circuits Syst. II Express Briefs, 2022
A Systematic and Generic Correlation-Based Design Approach for Data Sample Reduction in ML-Training.
Proceedings of the IEEE International Conference on Consumer Electronics - Taiwan, 2022
Design Methodology of Queue-Based Fast Classification for Sequential Minimal Optimization in SVM ML-Training.
Proceedings of the IEEE International Conference on Consumer Electronics - Taiwan, 2022
Design and Analysis of 7x7 Median Filter with 8-Step Low-Complexity Fast Searching Approach for Undersea Image Processing Applications.
Proceedings of the IEEE International Conference on Consumer Electronics - Taiwan, 2022
Scalable and Reconfigurable Architecture of Modified KD-Tree ML-Classifier with 5-Point Searching.
Proceedings of the IEEE International Conference on Consumer Electronics - Taiwan, 2022
2019
Flexible design and implementation of QC-Based LDPC decoder architecture for on-line user-defined matrix downloading and efficient decoding.
Integr., 2019
VLSI Architecture of 36-Mode Reconfigurable FFT Hardware Chip with Newly-Developed 2D-FIFO Arrangement Structure.
Proceedings of the 6th International Conference on Systems and Informatics, 2019
Design and Analysis of Cost-Efficient Ultra-High-Order Matched Filter Architecture Using 4-Phase Calculating Paths for Underwater Applications.
Proceedings of the IEEE International Conference on Consumer Electronics - Taiwan, 2019
2018
Design and Implementation of Flexible and Reconfigurable SDF-Based FFT Chip Architecture With Changeable-Radix Processing Elements.
IEEE Trans. Circuits Syst. I Regul. Pap., 2018
VLSI Design and Implementation of Reconfigurable 46-Mode Combined-Radix-Based FFT Hardware Architecture for 3GPP-LTE Applications.
IEEE Trans. Circuits Syst. I Regul. Pap., 2018
VLSI design and implementation of a reconfigurable hardware-friendly Polar encoder architecture for emerging high-speed 5G system.
Integr., 2018
Reconfigurable VLSI design of a changeable hybrid-radix FFT hardware architecture with 2D-FIFO storing structure for 3GPP LTE systems.
ICT Express, 2018
2017
48-Mode Reconfigurable Design of SDF FFT Hardware Architecture Using Radix-3<sup>2</sup> and Radix-2<sup>3</sup> Design Approaches.
IEEE Trans. Circuits Syst. I Regul. Pap., 2017
Reconfigurable hardware design of low-area-cost computing kernel engine for different radixes of single-path delay feedback FFT systems.
Proceedings of the IEEE International Conference on Consumer Electronics, 2017
Cost-efficient hardware design of coarse and fine rotation based FFT twiddle factor generator for 3GPP LTE applications.
Proceedings of the IEEE 6th Global Conference on Consumer Electronics, 2017
A 2-D grouping FIFO based hardware architecture for supporting 36-mode hybrid-radix FFT design in 3GPP-LTE systems.
Proceedings of the IEEE 6th Global Conference on Consumer Electronics, 2017
2016
High-speed low-area-cost VLSI design of polar codes encoder architecture using radix-k processing engines.
Proceedings of the IEEE 5th Global Conference on Consumer Electronics, 2016
Reconfigurable VLSI design of processing kernel for multiple-radix single-path delay feedback FFT systems.
Proceedings of the IEEE 5th Global Conference on Consumer Electronics, 2016
LEGO-based VLSI design and implementation of polar codes encoder architecture with radix-2 processing engines.
Proceedings of the 2016 IEEE Asia Pacific Conference on Circuits and Systems, 2016
2014
IEEE Trans. Circuits Syst. I Regul. Pap., 2014
2013
A 0.27mm<sup>2</sup> 13.5dBm 2.4GHz all-digital polar transmitter using 34%-efficiency Class-D DPA in 40nm CMOS.
Proceedings of the 2013 IEEE International Solid-State Circuits Conference, 2013
2012
Matrix Merging Scheme and Efficient Decoding Techniques for Reconfigurable QC-LDPC Decoders.
J. Signal Process. Syst., 2012
2009
Proceedings of the IEEE Workshop on Signal Processing Systems, 2009
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2009), 2009
Proceedings of the 14th Asia South Pacific Design Automation Conference, 2009
2008
An 8.29 mm<sup>2</sup> 52 mW Multi-Mode LDPC Decoder Design for Mobile WiMAX System in 0.13 µm CMOS Process.
IEEE J. Solid State Circuits, 2008
Proceedings of the IEEE International Conference on Acoustics, 2008