Weiran Kong

According to our database1, Weiran Kong authored at least 9 papers between 2008 and 2019.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of five.

Timeline

Legend:

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PhD thesis 
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Links

On csauthors.net:

Bibliography

2019
Demonstration of improvement of specific on-resistance versus breakdown voltage tradeoff for low-voltage power LDMOS.
Microelectron. J., 2019

2018
A 280-KBytes Twin-Bit-Cell Embedded NOR Flash Memory With a Novel Sensing Current Protection Enhanced Technique and High-Voltage Generating Systems.
IEEE Trans. Circuits Syst. II Express Briefs, 2018

Investigation and impact of LDD variations on the drain disturb in normally-on SONOS NOR flash device.
Microelectron. Reliab., 2018

2017
Investigation of read disturb in split-gate memory and its feasible solution.
Microelectron. Reliab., 2017

A duplex current-reused CMOS LNA with complementary derivative superposition technique.
Int. J. Circuit Theory Appl., 2017

Area-efficient charge pump with local boost technique for embedded flash memory.
IEICE Electron. Express, 2017

2016
Design Techniques for a 30-ns Access Time 1.5-V 200-KB Embedded EEPROM Memory.
IEEE Trans. Circuits Syst. II Express Briefs, 2016

A 0.5-V novel complementary current-reused CMOS LNA for 2.4 GHz medical application.
Microelectron. J., 2016

2008
Investigation of charge trapping/de-trapping induced operation lifetime degradation in triple SuperFlash<sup>®</sup> memory cell.
Microelectron. Reliab., 2008


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