Vinay Dabholkar

According to our database, Vinay Dabholkar authored at least 4 papers between 1995 and 1998.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

1998

Techniques for minimizing power dissipation in scan and combinational circuits during test application.

Vinay Dabholkar, Sreejit Chakravarty, Irith Pomeranz, Sudhakar M. Reddy

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1998

Computing Stress Tests for Gate Oxide Shorts.

Vinay Dabholkar, Sreejit Chakravarty

Proceedings of the 11th International Conference on VLSI Design (VLSI Design 1991), 1998

1997

Computing stress tests for interconnect defects.

Vinay Dabholkar, Sreejit Chakravarty

Proceedings of the 6th Asian Test Symposium (ATS '97), 17-18 November 1997, 1997

1995

Cyclic stress tests for full scan circuits.

Vinay Dabholkar, Sreejit Chakravarty, J. Najm, Janak H. Patel

Proceedings of the 13th IEEE VLSI Test Symposium (VTS'95), April 30, 1995