Valerio Tenace

According to our database, Valerio Tenace authored at least 23 papers between 2012 and 2021.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2021

Logic Synthesis Meets Machine Learning: Trading Exactness for Generalization.

Shubham Rai, Walter Lau Neto, Yukio Miyasaka, Xinpei Zhang, Mingfei Yu, Qingyang Yi, Masahiro Fujita, Guilherme B. Manske, Matheus F. Pontes, Leomar S. da Rosa, Marilton S. de Aguiar, Paulo F. Butzen, Po-Chun Chien, Yu-Shan Huang, Hoa-Ren Wang, Jie-Hong R. Jiang, Jiaqi Gu, Zheng Zhao, Zixuan Jiang, David Z. Pan, Brunno A. Abreu, Isac de Souza Campos, Augusto Andre Souza Berndt, Cristina Meinhardt, Jônata Tyska Carvalho, Mateus Grellert, Sergio Bampi, Aditya Lohana, Akash Kumar, Wei Zeng, Azadeh Davoodi, Rasit Onur Topaloglu, Yuan Zhou, Jordan Dotzel, Yichi Zhang, Hanyu Wang, Zhiru Zhang, Valerio Tenace, Pierre-Emmanuel Gaillardon, Alan Mishchenko, Satrajit Chatterjee

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2021

NEMO-CNN: An Efficient Near-Memory Accelerator for Convolutional Neural Networks.

Grant Brown, Valerio Tenace, Pierre-Emmanuel Gaillardon

Proceedings of the 32nd IEEE International Conference on Application-specific Systems, 2021

2020

Logic Synthesis of Pass-Gate Logic Circuits With Emerging Ambipolar Technologies.

Valerio Tenace, Andrea Calimera, Enrico Macii, Massimo Poncino

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020

2019

Layer-Wise Compressive Training for Convolutional Neural Networks.

Matteo Grimaldi, Valerio Tenace, Andrea Calimera

Future Internet, 2019

SAID: A Supergate-Aided Logic Synthesis Flow for Memristive Crossbars.

Valerio Tenace, Roberto Giorgio Rizzo, Debjyoti Bhattacharjee, Anupam Chattopadhyay, Andrea Calimera

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2019

Energy-Efficient Convolutional Neural Networks via Recurrent Data Reuse.

Luca Mocerino, Valerio Tenace, Andrea Calimera

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2019

2018

Quasi-exact logic functions through classification trees.

Valerio Tenace, Andrea Calimera

Integr., 2018

Inferential Logic: a Machine Learning Inspired Paradigm for Combinational Circuits.

Valerio Tenace, Andrea Calimera

Proceedings of the IFIP/IEEE International Conference on Very Large Scale Integration, 2018

Multiplication by Inference using Classification Trees: A Case-Study Analysis.

Roberto Giorgio Rizzo, Valerio Tenace, Andrea Calimera

Proceedings of the IEEE International Symposium on Circuits and Systems, 2018

A compression-driven training framework for embedded deep neural networks.

Matteo Grimaldi, Federico Pugliese, Valerio Tenace, Andrea Calimera

Proceedings of the Workshop on INTelligent Embedded Systems Architectures and Applications, 2018

2017

Activation-Kernel Extraction through Machine Learning.

Valerio Tenace, Andrea Calimera

Proceedings of the New Generation of CAS, 2017

2016

CAD Tools for Graphene-Based Electronic Circuits.

Valerio Tenace

PhD thesis, 2016

Quasi-Adiabatic Logic Arrays for Silicon and Beyond-Silicon Energy-Efficient ICs.

Valerio Tenace, Andrea Calimera, Enrico Macii, Massimo Poncino

IEEE Trans. Circuits Syst. II Express Briefs, 2016

Logic Synthesis for Silicon and Beyond-Silicon Multi-gate Pass-Logic Circuits.

Valerio Tenace, Andrea Calimera, Enrico Macii, Massimo Poncino

Proceedings of the VLSI-SoC: System-on-Chip in the Nanoscale Era - Design, Verification and Reliability, 2016

Multi-function logic synthesis of silicon and beyond-silicon ultra-low power pass-gates circuits.

Valerio Tenace, Andrea Calimera, Enrico Macii, Massimo Poncino

Proceedings of the 2016 IFIP/IEEE International Conference on Very Large Scale Integration, 2016

Enabling quasi-adiabatic logic arrays for silicon and beyond-silicon technologies.

Valerio Tenace, Andrea Calimera, Enrico Macii, Massimo Poncino

Proceedings of the IEEE International Symposium on Circuits and Systems, 2016

Graphene-PLA (GPLA): a Compact and Ultra-Low Power Logic Array Architecture.

Valerio Tenace, Andrea Calimera, Enrico Macii, Massimo Poncino

Proceedings of the 26th edition on Great Lakes Symposium on VLSI, 2016

2015

Ultra-low power circuits using graphene p-n junctions and adiabatic computing.

Sandeep Miryala, Valerio Tenace, Andrea Calimera, Enrico Macii, Massimo Poncino

Microprocess. Microsystems, 2015

Exploiting the Expressive Power of Graphene Reconfigurable Gates via Post-Synthesis Optimization.

Sandeep Miryala, Valerio Tenace, Andrea Calimera, Enrico Macii, Massimo Poncino, Luca Gaetano Amarù, Giovanni De Micheli, Pierre-Emmanuel Gaillardon

Proceedings of the 25th edition on Great Lakes Symposium on VLSI, GLVLSI 2015, Pittsburgh, PA, USA, May 20, 2015

One-pass logic synthesis for graphene-based Pass-XNOR logic circuits.

Valerio Tenace, Andrea Calimera, Enrico Macii, Massimo Poncino

Proceedings of the 52nd Annual Design Automation Conference, 2015

2014

Row-based body-bias assignment for dynamic thermal clock-skew compensation.

Valerio Tenace, Sandeep Miryala, Andrea Calimera, Alberto Macii, Enrico Macii, Massimo Poncino

Microelectron. J., 2014

Pass-XNOR logic: A new logic style for P-N junction based graphene circuits.

Valerio Tenace, Andrea Calimera, Enrico Macii, Massimo Poncino

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2014

2012

NBTI effects on tree-like clock distribution networks.

Wei Liu, Sandeep Miryala, Valerio Tenace, Andrea Calimera, Enrico Macii, Massimo Poncino

Proceedings of the Great Lakes Symposium on VLSI 2012, 2012