Utsav Banerjee
Orcid: 0000-0001-7949-4178
According to our database1,
Utsav Banerjee
authored at least 26 papers
between 2017 and 2024.
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Bibliography
2024
A 1.54-mm<sup>2</sup>, 264-GHz Wake-Up Receiver With Integrated Cryptographic Authentication for Ultra-Miniaturized Platforms.
IEEE J. Solid State Circuits, March, 2024
2023
A Threshold Implementation-Based Neural Network Accelerator With Power and Electromagnetic Side-Channel Countermeasures.
IEEE J. Solid State Circuits, 2023
CoRR, 2023
Energy-Efficient Cryptographic Acceleration using Hardware-Software Co-Design with RISC-V.
Proceedings of the IEEE International Symposium on Smart Electronic Systems, 2023
Tyche: A Compact and Configurable Accelerator for Scalable Probabilistic Computing on FPGA.
Proceedings of the IEEE High Performance Extreme Computing Conference, 2023
Privacy-Preserving Edge Computing from Pairing-Based Inner Product Functional Encryption.
Proceedings of the IEEE Global Communications Conference, 2023
A 1.54mm<sup>2</sup> Wake-Up Receiver Based on THz Carrier Wave and Integrated Cryptographic Authentication.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2023
2022
Power-Based Side-Channel Attack for AES Key Extraction on the ATMega328 Microcontroller.
CoRR, 2022
A Low-Power BLS12-381 Pairing Crypto-Processor for Internet-of-Things Security Applications.
CoRR, 2022
A ThreshoId-ImpIementation-Based Neural-Network Accelerator Securing Model Parameters and Inputs Against Power Side-Channel Attacks.
Proceedings of the IEEE International Solid-State Circuits Conference, 2022
Design and Analysis of a Scalable and Efficient Quantum Circuit for LWE Matrix Arithmetic.
Proceedings of the IEEE 40th International Conference on Computer Design, 2022
Wireless, Batteryless, and Secure Implantable System-on-a-Chip for 1.37mmHg Strain Sensing with Bandwidth Reconfigurability for Cross-Tissue Adaptation.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2022
Embedded Software Implementation of Privacy Preserving Matrix Computation using Elliptic Curve Cryptography for IoT Applications.
Proceedings of the IEEE International Conference on Advanced Networks and Telecommunications Systems, 2022
2021
Efficient Algorithms, Protocols and Hardware Architectures for Next-Generation Cryptography in Embedded Systems.
PhD thesis, 2021
Leaky Nets: Recovering Embedded Neural Network Models and Inputs Through Simple Power and Timing Side-Channels - Attacks and Defenses.
IEEE Internet Things J., 2021
A Low-Power Elliptic Curve Pairing Crypto-Processor for Secure Embedded Blockchain and Functional Encryption.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2021
Proceedings of the 34th IEEE International Symposium on Computer-Based Medical Systems, 2021
2020
Accelerating Post-Quantum Cryptography using an Energy-Efficient TLS Crypto-Processor.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2020
Efficient Post-Quantum TLS Handshakes using Identity-Based Key Exchange from Lattices.
Proceedings of the 2020 IEEE International Conference on Communications, 2020
Proceedings of the 2020 IEEE Custom Integrated Circuits Conference, 2020
2019
IACR Trans. Cryptogr. Hardw. Embed. Syst., 2019
An Energy-Efficient Reconfigurable DTLS Cryptographic Engine for Securing Internet-of-Things Applications.
IEEE J. Solid State Circuits, 2019
Sapphire: A Configurable Crypto-Processor for Post-Quantum Lattice-based Protocols (Extended Version).
IACR Cryptol. ePrint Arch., 2019
An Energy-Efficient Configurable Lattice Cryptography Processor for the Quantum-Secure Internet of Things.
Proceedings of the IEEE International Solid- State Circuits Conference, 2019
2018
An energy-efficient reconfigurable DTLS cryptographic engine for End-to-End security in iot applications.
Proceedings of the 2018 IEEE International Solid-State Circuits Conference, 2018
2017
eeDTLS: Energy-Efficient Datagram Transport Layer Security for the Internet of Things.
Proceedings of the 2017 IEEE Global Communications Conference, 2017