Umer Farooq

Orcid: 0000-0002-5220-4908

Affiliations:
  • Dhofar University, College of Engineering, Electrical and Computer Engineering Department, Salalah, Oman
  • Universite Pierre et Marie Curie, Department of informatics and electronics, Paris, France (PhD 2011)


According to our database1, Umer Farooq authored at least 38 papers between 2008 and 2023.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

Legend:

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Online presence:

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Bibliography

2023
Prototyping using multi-FPGA platform: A novel and complete flow.
Microprocess. Microsystems, February, 2023

2021
Pre-Silicon Verification Using Multi-FPGA Platforms: A Review.
J. Electron. Test., 2021

2020
Exploring and optimizing partitioning of large designs for multi-FPGA based prototyping platforms.
Computing, 2020

SHealth: A Blockchain-Based Health System With Smart Contracts Capabilities.
IEEE Access, 2020

A Precoding Based Power Domain UFMC Waveform for 5G Multi-Access Edge Computing.
Proceedings of the Fifth International Conference on Fog and Mobile Edge Computing, 2020

2019
A framework for high-level simulation and optimization of fine-grained reconfigurable architectures.
Simul., 2019

On the comparison of memristor-transistor hybrid and transistor-only heterogeneous FPGAs.
J. King Saud Univ. Comput. Inf. Sci., 2019

Efficient adaptive framework for securing the Internet of Things devices.
EURASIP J. Wirel. Commun. Netw., 2019

A Low PAPR Universal Filtered Multi-Carrier System for 5G Machine Type Communications.
Proceedings of the 2019 Wireless Days, 2019

A Low PAPR DHT Precoding Based UFMC Scheme for 5G Communication Systems.
Proceedings of the 6th International Conference on Control, 2019

Securing Internet of Things (IoT) Through an Adaptive Framework.
Proceedings of the 16th International Multi-Conference on Systems, Signals & Devices, 2019

2018
Novel architectural space exploration environment for multi-FPGA based prototyping systems.
Microprocess. Microsystems, 2018

A scheduling based energy-aware core switching technique to avoid thermal threshold values in multi-core processing systems.
Microprocess. Microsystems, 2018

A hybrid precoding- and filtering-based uplink MC-LNOMA scheme for 5G cellular networks with reduced PAPR.
Trans. Emerg. Telecommun. Technol., 2018

Inter-FPGA interconnect topologies exploration for multi-FPGA systems.
Des. Autom. Embed. Syst., 2018

Locality-aware task scheduling for homogeneous parallel computing systems.
Computing, 2018

An Efficient Inter-FPGA Routing Exploration Environment for Multi-FPGA Systems.
IEEE Access, 2018

A Joint Filtering and Precoding Based Uplink MC-NOMA.
Proceedings of the 2018 International Symposium on Networks, Computers and Communications, 2018

Machine Learning For Security: The Case of Side-Channel Attack Detection at Run-time.
Proceedings of the 25th IEEE International Conference on Electronics, Circuits and Systems, 2018

2017
Comparative analysis of different AES implementation techniques for efficient resource usage and better performance of an FPGA.
J. King Saud Univ. Comput. Inf. Sci., 2017

Comparison of direct and switch-based inter-FPGA routing interconnect for multi-FPGA systems.
Proceedings of the International Conference on ReConFigurable Computing and FPGAs, 2017

A Framework for High Level Simulation and Optimization of Coarse-Grained Reconfigurable Architectures.
Proceedings of the Applied Reconfigurable Computing - 13th International Symposium, 2017

2016
Adaptive and ubiquitous video streaming over Wireless Mesh Networks.
J. King Saud Univ. Comput. Inf. Sci., 2016

Inter-FPGA routing environment for performance exploration of multi-FPGA systems.
Proceedings of the 2016 International Symposium on Rapid System Prototyping, 2016

Multiple FPGAs based prototyping and debugging with complete design flow.
Proceedings of the 11th International Design & Test Symposium, 2016

A novel heterogeneous FPGA architecture based on memristor-transistor hybrid approach.
Proceedings of the 2016 International Conference on Design and Technology of Integrated Systems in Nanoscale Era, 2016

Using Timing-Driven Inter-FPGA Routing for Multi-FPGA Prototyping Exploration.
Proceedings of the 2016 Euromicro Conference on Digital System Design, 2016

2015
A design-flow for high-level synthesis and resource estimation of reconfigurable architectures.
Proceedings of the 10th International Conference on Design & Technology of Integrated Systems in Nanoscale Era, 2015

2014
Exploration and optimization of heterogeneous interconnect fabric of 3D tree-based FPGA.
Proceedings of the 9th International Conference on Design & Technology of Integrated Systems in Nanoscale Era, 2014

2013
Exploration and optimization of a homogeneous tree-based application specific inflexible FPGA.
Microelectron. J., 2013

Exploration environment for 3D heterogeneous tree-based FPGA architectures (3D HT-FPGA).
Proceedings of the 2012 International Conference on Reconfigurable Computing and FPGAs, 2013

High performance 3-dimensional heterogeneous tree-based FPGA architectures (HT-FPGA).
Proceedings of the 10th FPGAworld Conference, 2013

2012
A new heterogeneous tree-based application specific FPGA and its comparison with mesh-based application specific FPGA.
Microprocess. Microsystems, 2012

2011
Exploration of Heterogeneous FPGA Architectures.
Int. J. Reconfigurable Comput., 2011

Comparison between Heterogeneous Mesh-Based and Tree-Based Application Specific FPGA.
Proceedings of the Reconfigurable Computing: Architectures, Tools and Applications, 2011

2009
FPGA Interconnect Topologies Exploration.
Int. J. Reconfigurable Comput., 2009

2008
The Effect of LUT and Cluster Size on a Tree Based FPGA Architecture.
Proceedings of the ReConFig'08: 2008 International Conference on Reconfigurable Computing and FPGAs, 2008

A new coarse-grained FPGA architecture exploration environment.
Proceedings of the 2008 International Conference on Field-Programmable Technology, 2008


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