Tsuyoshi Iwagaki

According to our database, Tsuyoshi Iwagaki authored at least 30 papers between 2003 and 2020.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2020

Transient Fault Tolerant State Assignment for Stochastic Computing Based on Linear Finite State Machines.

Hideyuki Ichihara, Motoi Fukuda, Tsuyoshi Iwagaki, Tomoo Inoue

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2020

2019

Compact and Accurate Digital Filters Based on Stochastic Computing.

Hideyuki Ichihara, Tatsuyoshi Sugino, Shota Ishii, Tsuyoshi Iwagaki, Tomoo Inoue

IEEE Trans. Emerg. Top. Comput., 2019

An Empirical Approach to RTL Scan Path Design Focusing on Structural Interpretation in Logic Synthesis.

Tsuyoshi Iwagaki, Sho Yuasa, Hideyuki Ichihara, Tomoo Inoue

Proceedings of the IEEE International Test Conference in Asia, 2019

State Encoding with Stochastic Numbers for Transient Fault Tolerant Linear Finite State Machines.

Hideyuki Ichihara, Yuki Maeda, Tsuyoshi Iwagaki, Tomoo Inoue

Proceedings of the 2019 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2019

2017

State assignment for fault tolerant stochastic computing with linear finite state machines.

Hideyuki Ichihara, Motoi Fukuda, Tsuyoshi Iwagaki, Tomoo Inoue

Proceedings of the International Test Conference in Asia, 2017

2015

Logic simplification by minterm complement for error tolerant application.

Hideyuki Ichihara, Tomoya Inaoka, Tsuyoshi Iwagaki, Tomoo Inoue

Proceedings of the 33rd IEEE International Conference on Computer Design, 2015

Designing area-efficient controllers for multi-cycle transient fault tolerant systems.

Tsuyoshi Iwagaki, Yutaro Ishimori, Hideyuki Ichihara, Tomoo Inoue

Proceedings of the 20th IEEE European Test Symposium, 2015

A practical approach for logic simplification based on fault acceptability for error tolerant application.

Hideyuki Ichihara, Junpei Kamei, Tsuyoshi Iwagaki, Tomoo Inoue

Proceedings of the 20th IEEE European Test Symposium, 2015

2014

Compact and accurate stochastic circuits with shared random number sources.

Hideyuki Ichihara, Shota Ishii, Daiki Sunamori, Tsuyoshi Iwagaki, Tomoo Inoue

Proceedings of the 32nd IEEE International Conference on Computer Design, 2014

Scheduling algorithm in datapath synthesis for long duration transient fault tolerance.

Tsuyoshi Iwagaki, Tatsuya Nakaso, Ryoko Ohkubo, Hideyuki Ichihara, Tomoo Inoue

Proceedings of the 2014 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2014

2013

A Transient Fault Tolerant Test Pattern Generator for On-line Built-in Self-Test.

Yuki Fukazawa, Tsuyoshi Iwagaki, Hideyuki Ichihara, Tomoo Inoue

Proceedings of the 22nd Asian Test Symposium, 2013

2012

Modeling economics of LSI design and manufacturing for test design selection.

Hideyuki Ichihara, Noboru Shimizu, Tsuyoshi Iwagaki, Tomoo Inoue

Proceedings of the 30th International IEEE Conference on Computer Design, 2012

Utilizing register transfer level false paths for circuit optimization with a logic synthesis tool.

Tsuyoshi Iwagaki, Takehiro Mikami, Hideyuki Ichihara, Tomoo Inoue

Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems, 2012

2011

Flexible Test Scheduling for an Asynchronous On-Chip Interconnect through Special Data Transfer.

Tsuyoshi Iwagaki, Eiri Takeda, Mineo Kaneko

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2011

Backward-Data-Direction Clocking and Relevant Optimal Register Assignment in Datapath Synthesis.

Keisuke Inoue, Mineo Kaneko, Tsuyoshi Iwagaki

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2011

Indirect detection of clock skew induced hold-time violations on functional paths using scan shift operations.

Tsuyoshi Iwagaki, Kewal K. Saluja

Proceedings of the 14th IEEE International Symposium on Design and Diagnostics of Electronic Circuits & Systems, 2011

2010

A Pseudo-Boolean Technique for Generating Compact Transition Tests with All-Output-Propagation Properties.

Tsuyoshi Iwagaki, Mineo Kaneko

Proceedings of the Fifth IEEE International Symposium on Electronic Design, 2010

2009

Optimal Register Assignment with Minimum-Path Delay Compensation for Variation-Aware Datapaths.

Keisuke Inoue, Mineo Kaneko, Tsuyoshi Iwagaki

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2009

On the derivation of a minimum test set in high quality transition testing.

Tsuyoshi Iwagaki, Mineo Kaneko

Proceedings of the 10th Latin American Test Workshop, 2009

Safe clocking for the setup and hold timing constraints in datapath synthesis.

Keisuke Inoue, Mineo Kaneko, Tsuyoshi Iwagaki

Proceedings of the 19th ACM Great Lakes Symposium on VLSI 2009, 2009

2008

Novel Register Sharing in Datapath for Structural Robustness against Delay Variation.

Keisuke Inoue, Mineo Kaneko, Tsuyoshi Iwagaki

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2008

Safe clocking register assignment in datapath synthesis.

Keisuke Inoue, Mineo Kaneko, Tsuyoshi Iwagaki

Proceedings of the 26th International Conference on Computer Design, 2008

2007

Efficient path delay test generation based on stuck-at test generation using checker circuitry.

Tsuyoshi Iwagaki, Satoshi Ohtake, Mineo Kaneko, Hideo Fujiwara

Proceedings of the 2007 International Conference on Computer-Aided Design, 2007

2006

A Low Power Deterministic Test Using Scan Chain Disable Technique.

Zhiqiang You, Tsuyoshi Iwagaki, Michiko Inoue, Hideo Fujiwara

IEICE Trans. Inf. Syst., 2006

Broadside Transition Test Generation for Partial Scan Circuits through Stuck-at Test Generation.

Tsuyoshi Iwagaki, Satoshi Ohtake, Hideo Fujiwara

Proceedings of the VLSI-SoC: Research Trends in VLSI and Systems on Chip, 2006

A New Test Generation Model for Broadside Transition Testing of Partial Scan Circuits.

Tsuyoshi Iwagaki, Satoshi Ohtake, Hideo Fujiwara

Proceedings of the IFIP VLSI-SoC 2006, 2006

2005

Acceleration of transition test generation for acyclic sequential circuits utilizing constrained combinational stuck-at test generation.

Tsuyoshi Iwagaki, Satoshi Ohtake, Hideo Fujiwara

Proceedings of the 10th European Test Symposium, 2005

Efficient Constraint Extraction for Template-Based Processor Self-Test Generation.

Kazuko Kambe, Michiko Inoue, Hideo Fujiwara, Tsuyoshi Iwagaki

Proceedings of the 14th Asian Test Symposium (ATS 2005), 2005

2004

A design methodology to realize delay testable controllers using state transition information.

Tsuyoshi Iwagaki, Satoshi Ohtake, Hideo Fujiwara

Proceedings of the 9th European Test Symposium, 2004

2003

Reducibility of Sequential Test Generation to Combinational Test Generation for Several Delay Fault Models.

Tsuyoshi Iwagaki, Satoshi Ohtake, Hideo Fujiwara

Proceedings of the 12th Asian Test Symposium (ATS 2003), 17-19 November 2003, Xian, China, 2003