Tingyuan Liang

According to our database, Tingyuan Liang authored at least 16 papers between 2017 and 2024.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2024

GraFlex: Flexible Graph Processing on FPGAs through Customized Scalable Interconnection Network.

Chunyou Su, Linfeng Du, Tingyuan Liang, Zhe Lin, Maolin Wang, Sharad Sinha, Wei Zhang

Proceedings of the 2024 ACM/SIGDA International Symposium on Field Programmable Gate Arrays, 2024

2023

HL-Pow: Learning-Assisted Pre-RTL Power Modeling and Optimization for FPGA HLS.

Zhe Lin, Tingyuan Liang, Jieru Zhao, Sharad Sinha, Wei Zhang

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., November, 2023

MiniTNtk: An Exact Synthesis-based Method for Minimizing Transistor Network.

Weihua Xiao, Shanshan Han, Yue Yang, Shaoze Yang, Cheng Zheng, Jingsong Chen, Tingyuan Liang, Lei Li, Weikang Qian

Proceedings of the IEEE/ACM International Conference on Computer Aided Design, 2023

DiffLo: A Graph-based Method for Functional Discrepancy Localization in High-level Synthesis.

Liangji Chen, Tingyuan Liang, Wei Zhang, Sharad Sinha

Proceedings of the International Conference on Field Programmable Technology, 2023

FADO: Floorplan-Aware Directive Optimization for High-Level Synthesis Designs on Multi-Die FPGAs.

Linfeng Du, Tingyuan Liang, Sharad Sinha, Zhiyao Xie, Wei Zhang

Proceedings of the 2023 ACM/SIGDA International Symposium on Field Programmable Gate Arrays, 2023

PROPHET: Predictive On-Chip Power Meter in Hardware Accelerator for DNN.

Jian Peng, Tingyuan Liang, Zhiyao Xie, Wei Zhang

Proceedings of the 60th ACM/IEEE Design Automation Conference, 2023

2022

AMF-Placer 2.0: Open Source Timing-driven Analytical Mixed-size Placer for Large-scale Heterogeneous FPGA.

Tingyuan Liang, Gengjie Chen, Jieru Zhao, Sharad Sinha, Wei Zhang

CoRR, 2022

AutoCellLibX: Automated Standard Cell Library Extension Based on Pattern Mining.

Tingyuan Liang, Jingsong Chen, Lei Li, Wei Zhang

CoRR, 2022

2021

AMF-Placer: High-Performance Analytical Mixed-size Placer for FPGA.

Tingyuan Liang, Gengjie Chen, Jieru Zhao, Sharad Sinha, Wei Zhang

Proceedings of the IEEE/ACM International Conference On Computer Aided Design, 2021

2020

FP-Stereo: Hardware-Efficient Stereo Vision for Embedded Applications.

Jieru Zhao, Tingyuan Liang, Liang Feng, Wenchao Ding, Sharad Sinha, Wei Zhang, Shaojie Shen

Proceedings of the 30th International Conference on Field-Programmable Logic and Applications, 2020

2019

Hi-ClockFlow: Multi-Clock Dataflow Automation and Throughput Optimization in High-Level Synthesis.

Tingyuan Liang, Jieru Zhao, Liang Feng, Sharad Sinha, Wei Zhang

Proceedings of the International Conference on Computer-Aided Design, 2019

A Hybrid Data-Consistent Framework for Link-Aware AccessManagement in Emerging CPU-FPGA Platforms.

Liang Feng, Jieru Zhao, Tingyuan Liang, Sharad Sinha, Wei Zhang

Proceedings of the 2019 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, 2019

Machine Learning Based Routing Congestion Prediction in FPGA High-Level Synthesis.

Jieru Zhao, Tingyuan Liang, Sharad Sinha, Wei Zhang

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2019

LAMA: Link-Aware Hybrid Management for Memory Accesses in Emerging CPU-FPGA Platforms.

Liang Feng, Jieru Zhao, Tingyuan Liang, Sharad Sinha, Wei Zhang

Proceedings of the 56th Annual Design Automation Conference 2019, 2019

2018

Hi-DMM: High-Performance Dynamic Memory Management in High-Level Synthesis.

Tingyuan Liang, Jieru Zhao, Liang Feng, Sharad Sinha, Wei Zhang

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2018

2017

PAAS: A system level simulator for heterogeneous computing architectures.

Tingyuan Liang, Liang Feng, Sharad Sinha, Wei Zhang

Proceedings of the 27th International Conference on Field Programmable Logic and Applications, 2017