Tianpei Zhang

According to our database, Tianpei Zhang authored at least 8 papers between 2002 and 2009.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2009

Substrate Topological Routing for High-Density Packages.

Shenghua Liu, Guoqiang Chen, Tom Tong Jing, Lei He, Tianpei Zhang, Robi Dutta, Xianlong Hong

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2009

2008

Buffering global interconnects in structured ASIC design.

Tianpei Zhang, Sachin S. Sapatnekar

Integr., 2008

Topological routing to maximize routability for package substrate.

Shenghua Liu, Guoqiang Chen, Tom Tong Jing, Lei He, Tianpei Zhang, Robi Dutta, Xianlong Hong

Proceedings of the 45th Design Automation Conference, 2008

2007

Simultaneous Shield and Buffer Insertion for Crosstalk Noise Reduction in Global Routing.

Tianpei Zhang, Sachin S. Sapatnekar

IEEE Trans. Very Large Scale Integr. Syst., 2007

Module assignment for pin-limited designs under the stacked-Vdd paradigm.

Yong Zhan, Tianpei Zhang, Sachin S. Sapatnekar

Proceedings of the 2007 International Conference on Computer-Aided Design, 2007

2006

Temperature-aware routing in 3D ICs.

Tianpei Zhang, Yong Zhan, Sachin S. Sapatnekar

Proceedings of the 2006 Conference on Asia South Pacific Design Automation: ASP-DAC 2006, 2006

2005

Placement and Routing in 3D Integrated Circuits.

Cristinel Ababei, Yan Feng, Brent Goplen, Hushrav Mogal, Tianpei Zhang, Kia Bazargan, Sachin S. Sapatnekar

IEEE Des. Test Comput., 2005

2002

Optimized pin assignment for lower routing congestion after floorplanning phase.

Tianpei Zhang, Sachin S. Sapatnekar

Proceedings of the Fourth IEEE/ACM International Workshop on System-Level Interconnect Prediction (SLIP 2002), 2002