Theodore W. Manikas

Orcid: 0000-0001-8331-9815

According to our database1, Theodore W. Manikas authored at least 32 papers between 2002 and 2024.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

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Links

On csauthors.net:

Bibliography

2024
Dual Use Circuitry for Early Failure Warning and Test.
Proceedings of the 25th International Symposium on Quality Electronic Design, 2024

2023
Increased Detection of Hard-to-Detect Stuck-at Faults during Scan Shift.
J. Electron. Test., April, 2023

CNN-Assisted Steganography - Integrating Machine Learning with Established Steganographic Techniques.
CoRR, 2023

Harvesting Wasted Clock Cycles for Efficient Online Testing.
Proceedings of the IEEE European Test Symposium, 2023

2021
3D Ring Oscillator Based Test Structures to Detect a Trojan Die in a 3D Die Stack in the Presence of Process Variations.
IEEE Trans. Emerg. Top. Comput., 2021

Low Power Shift and Capture through ATPG-Configured Embedded Enable Capture Bits.
Proceedings of the IEEE International Test Conference, 2021

Industrial Control System Anomaly Detection Using Convolutional Neural Network Consensus.
Proceedings of the IEEE Conference on Control Technology and Applications, 2021

2019
Repurposing FPGAs for Tester Design to Enhance Field-Testing in a 3D Stack.
J. Electron. Test., 2019

Test Architecture for Fine Grained Capture Power Reduction.
Proceedings of the 26th IEEE International Conference on Electronics, Circuits and Systems, 2019

2017
Automated Markov-chain based analysis for large state spaces.
Proceedings of the 2017 Annual IEEE International Systems Conference, 2017

Detecting a trojan die in 3D stacked integrated circuits.
Proceedings of the 2017 IEEE North Atlantic Test Workshop, 2017

2016
Reliability block diagram extensions for non-parametric probabilistic analysis.
Proceedings of the Annual IEEE Systems Conference, 2016

Using Existing Reconfigurable Logic in 3D Die Stacks for Test.
Proceedings of the 25th IEEE North Atlantic Test Workshop, 2016

2015
Repairing a 3-D Die-Stack Using Available Programmable Logic.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2015

Modeling System Threat Probabilities Using Mixed-Radix Multiple-Valued Logic Decision Diagrams.
J. Multiple Valued Log. Soft Comput., 2015

Edge Reduction for EVMDDs to Speed Up Analysis of Multi-state Systems.
Proceedings of the 2015 IEEE International Symposium on Multiple-Valued Logic, 2015

2014
On Optimizations of Edge-Valued MDDs for Fast Analysis of Multi-State Systems.
IEICE Trans. Inf. Syst., 2014

System Probability Distribution Modeling Using MDDs.
Proceedings of the IEEE 44th International Symposium on Multiple-Valued Logic, 2014

Analysis Methods of Multi-state Systems Partially Having Dependent Components Using Multiple-Valued Decision Diagrams.
Proceedings of the IEEE 44th International Symposium on Multiple-Valued Logic, 2014

2013
Spectral Response of Ternary Logic Netlists.
Proceedings of the 43rd IEEE International Symposium on Multiple-Valued Logic, 2013

Embedded and real-time systems classes in traditional and distance education format.
Proceedings of the IEEE Frontiers in Education Conference, 2013

Built-in Self-Repair in a 3D die stack using programmable logic.
Proceedings of the 2013 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2013

2012
Integrated Circuit Channel Routing using a Pareto-Optimal Genetic Algorithm.
J. Circuits Syst. Comput., 2012

Modeling Medical System Threats with Conditional Probabilities Using Multiple-Valued Logic Decision Diagrams.
Proceedings of the 42nd IEEE International Symposium on Multiple-Valued Logic, 2012

2011
Using Multiple-Valued Logic Decision Diagrams to Model System Threat Probabilities.
Proceedings of the 41st IEEE International Symposium on Multiple-Valued Logic, 2011

2010
An Electrical Engineering Summer Academy for Middle School and High School Students.
IEEE Trans. Educ., 2010

On-chip thermal optimisation by whitespace reallocation using a constrained particleswarm optimisation algorithm.
IET Circuits Devices Syst., 2010

2009
A Genetic Algorithm for Autonomous Navigation Using Variable-Monotone Paths.
Int. J. Robotics Autom., 2009

2008
Multiple-Valued Logic Memory System Design Using Nanoscale Electrochemical Cells.
Proceedings of the 38th IEEE International Symposium on Multiple-Valued Logic (ISMVL 2008), 2008

2006
Evolving A Diverse Collection of Robot Path Planning Problems.
Proceedings of the IEEE International Conference on Evolutionary Computation, 2006

2004
Autonomous local path planning for a mobile robot using a genetic algorithm.
Proceedings of the IEEE Congress on Evolutionary Computation, 2004

2002
Partitioning Effects on Estimated Wire Length for Mixed Macro and Standard Cell Placement.
Proceedings of the 11th IEEE/ACM International Workshop on Logic & Synthesis, 2002


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